NXP Semiconductors MPC5606S - Destructive Event Reset Disable Register (RGM_DERD)

Reset Generation Module (MC_RGM)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1081
31.3.1.4 Destructive Event Reset Disable Register (RGM_DERD)
This register provides dedicated bits to disable particular destructive reset sources. When a destructive
reset source is disabled, the associated destructive event will trigger either a safe mode request or an
interrupt request (see
Section 31.3.1.6, Destructive Event Alternate Request Register (RGM_DEAR)). It
can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read only in user
mode. Each byte can be written only once after power-on reset.
D_SOFT Disable software reset
0 A software reset event triggers a reset sequence
1 A software reset event generates either a Safe mode or an interrupt request depending on the value of
RGM_FEAR.AR_SOFT
D_CORE Disable core reset
0 A core reset event triggers a reset sequence
1 A core reset event generates either a Safe mode or an interrupt request depending on the value of
RGM_FEAR.AR_CORE
D_JTAG Disable JTAG initiated reset
0 A JTAG initiated reset event triggers a reset sequence
1 A JTAG initiated reset event generates either a Safe mode or an interrupt request depending on the value of
RGM_FEAR.AR_JTAG
Address 0xC3FE_4006 Access: Supervisor read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0
D_LVD27
D_SWT
D_LVD12_PD1 D_LVD12_PD0
W
POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-5. Destructive Event Reset Disable Register (RGM_DERD)
Table 31-5. Functional Event Reset Disable Register (RGM_FERD) field descriptions (continued)
Field Description