Interrupt Controller (INTC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 757
The INTC_CPR masks any peripheral or software settable interrupt request set at the same or lower
priority as the current value of the INTC_CPR[PRI] field from generating an interrupt request to the
processor. When the INTC interrupt acknowledge register (INTC_IACKR) is read in software vector
mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode, the
value of PRI is pushed onto the LIFO, and PRI is updated with the priority of the preempting interrupt
request. When the INTC end-of-interrupt register (INTC_EOIR) is written, the LIFO is popped into the
INTC_CPR’s PRI field.
The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to
Section 21.7.5, Priority Ceiling Protocol.
NOTE
A store to modify the PRI field that closely precedes or follows an access to
a shared resource can result in a non-coherent access to the resource. Refer
to Section 21.7.5.2, Ensuring Coherency, for example code to ensure
coherency.
Offset: 0x0008 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Figure 21-3. INTC Current Priority Register (INTC_CPR)
Table 21-4. INTC_CPR field descriptions
Field Description
28–31
PRI[0:3]
Priority. PRI is the priority of the currently executing ISR according to the field values defined in
Tabl e 21-5.
Table 21-5. PRI Values
PRI Meaning
1111 Priority 15—highest priority
1110 Priority 14
1101 Priority 13
1100 Priority 12
1011 Priority 11
1010 Priority 10
1001 Priority 9
1000 Priority 8
0111 Priority 7
To Next Page
Loading...
