NXP Semiconductors MPC5606S - Page 374

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
372 Freescale Semiconductor
Figure 12-21. Interrupt Status Register (INT_STATUS)
Offset: 0x1EC Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0 0 0 0 0
P4_FIFO_HI_FLAG
P4_FIFO_LO_FLAG
P3_FIFO_HI_FLAG
P3_FIFO_LO_FLAG
W w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
DMA_TRANS_FINISH
0 0
IPM_ERROR
PROG_END
P2_FIFO_HI_FLAG
P2_FIFO_LO_FLAG
P1_FIFO_HI_FLAG
P1_FIFO_LO_FLAG
CRC_OVERFLOW
CRC_READY
VS_BLANK
LS_BF_VS
UNDRUN
VSYNC
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 12-23. INT_STATUS field descriptions
Field Description
12
P4_FIFO_HI_FLAG
Interrupt signal that indicates the High threshold has been reached for plane 4(FG2plane)
input buffer
13
P4_FIFO_LO_FLAG
Interrupt signal that indicates the Low threshold has been reached for plane 4(FG2plane)
input buffer
14
P3_FIFO_HI_FLAG
Interrupt signal that indicates the High threshold has been reached for plane 3(FG1plane)
input buffer
15
P3_FIFO_LO_FLAG
Interrupt signal that indicates the Low threshold has been reached for plane 3(FG1plane)
input buffer
17
DMA_TRANS_FINISH
Interrupt signal that indicates that the DCU DMA has fetched the last pixel of data from
the memory
20
IPM_ERROR
Interrupt signal that indicates that an error has occurred in the Magenta line transaction
21
PROG_END
Interrupt signal that indicates that the duration for programming of DCU registers and
internal memories is finished
22
P2_FIFO_HI_FLAG
Interrupt signal that indicates the High threshold has been reached for plane 2 (FGplane)
input buffer