Safety
MPC5606S Microcontroller Reference Manual, Rev. 7
128 Freescale Semiconductor
if the SWT_TO register is set to 5000 and SWT_WN register is set to 1000 then the service sequence must
be performed in the last 20% of the timeout period. There is a short lag in the time it takes for the window
to open due to synchronization logic in the watchdog design. This delay could be up to three system plus
four counter clock cycles.
The interrupt then reset bit SWT_CR[ITR] controls the action taken when a timeout occurs. If the
SWT_CR[ITR] bit is not set, a reset is generated immediately on a timeout. If the SWT_CR[ITR] bit is
set, an initial timeout causes the SWT to generate an interrupt and load the down counter with the timeout
period. If the service sequence is not written before the second consecutive timeout, the SWT generates a
system reset. The interrupt is indicated by the timeout interrupt flag SWT_IR[TIF]. The interrupt request
is cleared by writing a one to the SWT_IR[TIF] bit.
The SWT_CO register shows the value of the down counter when the watchdog is disabled. When the
watchdog is enabled this register is cleared. The value shown in this register can lag behind the value in
the internal counter for up to six system plus eight counter clock cycles.
The SWT_CO can be used during a software self-test of the SWT. For example, the SWT can be enabled
and not serviced for a fixed period of time less than the timeout value. Then the SWT can be disabled
(SWT_CR[WEN] cleared) and the value of the SWT_CO read to determine if the internal down counter
is working properly.
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