Overview
MPC5606S Microcontroller Reference Manual, Rev. 7
52 Freescale Semiconductor
• Logic Unit (LU)
• 32-bit Barrel shifter (Shifter)
• Mask-Insertion Unit (MIU)
• Condition Register manipulation Unit (CRU)
• Count-Leading-Zeros unit (CLZ)
•8 × 32 hardware multiplier array
• Result feed-forward hardware
• Hardware divider
Most arithmetic and logical operations are executed in a single cycle with the exception of the divide and
multiply instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit
contains a PC incrementer and a dedicated Branch Address adder to minimize delays during change of
flow operations. Branch target prefetching from the BTB is performed to accelerate certain taken branches.
Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline.
Prefetched instructions are placed into an instruction buffer capable of holding four instructions.
Conditional branches not taken execute in a single clock. Branches with successful target prefetching have
an effective execution time of one clock on e200z0h. All other taken branches have an execution time of
two clocks.
Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic
zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These
instructions can be pipelined to allow effective single-cycle throughput. Load and store multiple word
instructions allow low overhead context save and restore operations. The load/store unit contains a
dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use
dependency does not incur any pipeline bubbles for most cases.
The Condition Register unit supports the condition register (CR) and condition register operations defined
by the Power Architecture. The condition register consists of eight 4-bit fields that reflect the results of
certain operations, such as:
•Move
• Integer and floating-point compare
• Arithmetic
• Logical instructions
and provide a mechanism for testing and branching.
Vectored and autovectored interrupts are supported. Hardware-vectored interrupt support is provided to
allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead.
The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This allows the
Power Architecture instruction set to be represented by a modified instruction set made up from a mixture
of 16-bit and 32-bit instructions. This results in a significantly smaller code size footprint without affecting
performance noticeably.
The CPU core is enhanced by an additional interrupt source, the Non-Maskable Interrupt (NMI). This
interrupt source is routed directly from package pins, via edge detection logic in the SIU to the CPU,
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