Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 921
SMR Safe mode request from MC_RGM is active indicator — This bit is set if a hardware Safe mode request has been
triggered. It is cleared when the hardware Safe mode request has been cleared.
0 A Safe mode request is not active
1 A Safe mode request is active
FMPLL0_SC FMPLL0 State Change during mode transition indicator — This bit is set when the primary frequency modulated
phase locked loop is requested to change its startup/shutdown state. It is cleared when the primary frequency
modulated phase locked loop has completed its state change.
0 No state change is taking place
1 A state change is taking place
FXOSC_SC FXOSC State Change during mode transition indicator — This bit is set when the fast external crystal oscillator
(4-16MHz) is requested to change its startup/shutdown state. It is cleared when the fast external crystal oscillator
(4-16MHz) has completed its state change.
0 No state change is taking place
1 A state change is taking place
FIRC_SC FIRC State Change during mode transition indicator — This bit is set when the fast internal RC oscillator
(16MHz) is requested to change its startup/shutdown state. It is cleared when the fast internal RC oscillator
(16MHz) has completed its state change.
0 No state change is taking place
1 A state change is taking place
SSCLK_SC Secondary System Clock Sources State Change during mode transition indicator — This bit is set when a
secondary system clock source is requested to change its startup/shutdown state. It is cleared when all
secondary system clock sources have completed their state changes. (A secondary system clock source is a
system clock source other than FIRC, FXOSC, or FMPLL0.)
0 No state change is taking place
1 A state change is taking place
SYSCLK_S
W
System Clock Switching pending status —
0 No system clock source switching is pending
1 A system clock source switching is pending
DFLASH_SC DFLASH State Change during mode transition indicator — This bit is set when the DFLASH is requested to
change its startup/shutdown state. It is cleared when the DFLASH has completed its state change.
0 No state change is taking place
1 A state change is taking place
CFLASH_SC CFLASH State Change during mode transition indicator — This bit is set when the CFLASH is requested to
change its startup/shutdown state. It is cleared when the DFLASH has completed its state change.
0 No state change is taking place
1 A state change is taking place
CDP_PRPH
_0_143
Clock Disable Process Pending status for Peripherals 0…143 — This bit is set when any peripheral has been
requested to have its clock disabled. It is cleared when all the peripherals which have been requested to have
their clocks disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
CDP_PRPH
_96_127
Clock Disable Process Pending status for Peripherals 96…127 — This bit is set when any peripheral appearing
in ME_PS3 has been requested to have its clock disabled. It is cleared when all these peripherals which have
been requested to have their clocks disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
Table 25-10. Debug Mode Transition Status Register (ME_DMTS) field descriptions (continued)
Field Description
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