NXP Semiconductors MPC5606S - Page 1169

Stepper Stall Detect (SSD)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1167
Figure 36-9. SSD block diagram, analog block
Main part of the analog block is the -modulator. It is operational during the BIS integration phase only
(step
5 in Section 36.4.2.2, Details of the SSD Measurement). The clock to update the feedback path is
derived from the bus clock using the ACDIV setting. The 1-bit output value provided to the digital part is
used to increment or decrement the ITGACC register.
Sine Coil
Cosine Coil
Bus
VDDM
COSP
COSM
T1
T2
T3
VSSM
VDDM
T4
VSSM
S1
S3
S2
S4
VDDM
SINP
SINM
T5
T6
T7
VSSM
VDDM
T8
VSSM
S5
S7
S6
S8
Offset
Cancellation
VDDM
VSSM
R2
R2
R1
C1
+
–
+
–
Down Counter
Load Register
sigma-delta modulator + ref. voltage generation
P
A
D
P
A
D
P
A
D
P
A
D
integrator
reference
DAC
Integration
Accumulator
Down Counter
Prescaler
Accumulator
Prescaler
DFF
SSD_1MOTanalog block
Clock signals
BIS
Control
Separate for Blanking and Integration
Shaded Down Counter Blocks:
+
–
Down Counter
OBE to pads
Clock