Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 507
is organized 64-bits in width to minimize the time needed to fetch the activated channel’s descriptor and
load it into the dma_engine.addr_path.channel_{x,y} registers.
Figure 15-34. DMA operation, part 1
In the second part of the basic data flow as shown in Figure 15-35, the modules associated with the data
transfer (addr_path, data_path and control) sequence through the required source reads and destination
writes to perform the actual data movement. The source reads are initiated and the fetched data is
temporarily stored in the data_path module until it is gated onto the AMBA-AHB bus during the
destination write. This source read/destination write processing continues until the inner minor byte count
has been transferred. The dma_ipd_done[n] signal is asserted at the end of the minor byte count transfer.
j
j+1
n-1
SRAM
Transfer
Control
Descriptor (TCD)
DMA engine
addr_path
data_path
DMA
IPS
Bus
AMBA
Bus
ipd_req[n-1:0]
dma_ipi_int[n-1:0]
0
c
o
n
t
r
o
l
pmodel_charb
addr
wdata[31:0]
rdata[31:0]
hrdata[{63,31}:0]
hwdata[{63,31}:0]
haddr[31:0]
dma_ipd_done[n-1:0]
To Next Page
Loading...
