NXP Semiconductors MPC5606S - Page 697

FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 695
When the FEN bit in the MCR is set (FIFO enabled), the function of the eight least significant interrupt
flags (BUF7I–BUF0I) is changed to support the FIFO operation. BUF7I, BUF6I, and BUF5I indicate
operating conditions of the FIFO, while BUF4I to BUF0I are not used.
Address: Base + 0x0030 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
BUF
31I
BUF
30I
BUF
29I
BUF
28I
BUF
27I
BUF
26I
BUF
25I
BUF
24I
BUF
23I
BUF
22I
BUF
21I
BUF
20I
BUF
19I
BUF
18I
BUF
17I
BUF
16I
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BUF
15I
BUF
14I
BUF
13I
BUF
12I
BUF
11I
BUF
10I
BUF
9I
BUF
8I
BUF
7I
BUF
6I
BUF
5I
BUF
4I
BUF
3I
BUF
2I
BUF
1I
BUF
0I
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-14. Interrupt Flag Register Low (IFRL)
Table 18-17. IFRL field descriptions
Field Description
BUF31I–BUF8I Buffer MB
i
Interrupt
Each bit flags the respective FlexCAN Message Buffer (MB8 to MB31) interrupt.
0 No such occurrence
1 The corresponding MB has successfully completed transmission or reception
BUF7I Buffer MB7 Interrupt or FIFO Overflow
If the FIFO is not enabled, this bit flags the interrupt for MB7. If the FIFO is enabled, this flag
indicates an overflow condition in the FIFO (frame lost because FIFO is full).
0 No such occurrence
1 MB7 completed transmission/reception or FIFO overflow
BUF6I Buffer MB6 Interrupt or FIFO Warning
If the FIFO is not enabled, this bit flags the interrupt for MB6. If the FIFO is enabled, this flag
indicates that four out of six buffers of the FIFO are already occupied (FIFO almost full).
0 No such occurrence
1 MB6 completed transmission/reception or FIFO almost full
BUF5I Buffer MB5 Interrupt or Frames available in FIFO
If the FIFO is not enabled, this bit flags the interrupt for MB5. If the FIFO is enabled, this flag
indicates that at least one frame is available to be read from the FIFO.
0 No such occurrence
1 MB5 completed transmission/reception or frames available in the FIFO
BUF4I–BUF0I Buffer MB
i
Interrupt or Reserved
If the FIFO is not enabled, these bits flag the interrupts for MB0 to MB4. If the FIFO is enabled,
these flags are not used and must be considered as reserved locations.
0 No such occurrence
1 Corresponding MB completed transmission/reception