Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 665
Table 17-70. General flash memory setting recommendations for 64 MHz system clock
1
Access Parameter
General Recommendations
Code flash (banks 0 and 2)
4 line buffers per port
Data flash (bank 1)
1 line buffer per port
Parameter
symbol
in register PFCR0
Comments
Parameter
symbolin register
PFCR1
Comments
Port 0
(Core only
Page Buffer Enable B0_P0_BFE = 1 Enable port’s
buffers
B1_P0_BFE = 1 Enable port’s buffer
Instruction Prefetch
Enable
B0_P0_IPFE = 1 Instructions are
mostly sequential,
so prefeching can
improve
performance.
— —
Data Prefetch
Enable
B0_P0_DPFE = 0 Data accesses are
expected to
generally be
random, not
sequential
— —
Prefetch Limit B0_P0_PFLIM = 3 Prefetch on hit or
miss
— —
Page Buffer
Configuration
B0_P0_BCFG = 3 Allocate 3 line
buffers for
instructions,
1 for data
— —
Port 1
(DCU,
eDMA)
Page Buffer Enable B0_P1_BFE = 1 Enable port’s
buffers
B1_P1_BFE = 1 Enable port’s buffer
Instruction Prefetch
Enable
B0_P1_IPFE = 0 No instruction
access on port 1
— —
Data Prefetch
Enable
B0_P1_DPFE = 1 Enable prefetching
assuming there is
significant
sequential data
— —
Prefetch Limit B0_P1_PFLIM = 1 Prefetch on miss
only (allows more
bandwidth for core)
— —
Page Buffer
Configuration
B0_P1_BCFG = 0 All 4 line buffers
available for any
access
— —
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