NXP Semiconductors MPC5606S - Page 636

Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
634 Freescale Semiconductor
Figure 17-42. Power Architecture e200z0h RPP reference platform block diagram
As shown in this block diagram, there are a number of baseline and optional modules (shaded) supported.
The module list includes:
• Power Architecture e200z0h core with Nexus1 or optional Nexus2+ debug
• Optional 16-channel second-generation Direct Memory Access (DMA)
• Optional off-platform bus master, e.g., FlexRay
• AHB crossbar switch (XBAR)
• Optional Memory Protection Unit (MPU)
• 2-port Platform Flash memory controller (PFLASH2P_LCA) with connections to 3 memory banks
• Platform RAM memory controller (PRAM)
• AHB-to-{IPS/APB} bus controller (PBRIDGE-Lite) for access to on- and off-platform slave
modules
• Interrupt Controller (INTC)
• 4-channel System Timers (STM)
• Software Watchdog Timer (SWT)
XBAR
MemArray
eDMA
Mem
s0
s2
m0
s7
MemArray
PRAM
PFLASH2P
IPS/APB
INTC
AHB BIU
Branch Unit
Load/Store
I-Fetcher
Dispatch
GPR
Integer
Unit
e200z0h Core
p_i_h*
p_d_h*
m1
m2
MPU
On-platform IRQs
Off-Platform IRQs
Debug
Unit
Nexus1,
Nexus2+
Off-Platform
Master
m3
STM
IPS Bus
IPS+APB Bus
Flash Regs
IPS+APB
Slave
Modules
MemArray
Flash Regs
Bank0
Bank1
ECSM
SWT
s1
MemArray
Flash Regs
Bank2