Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 635
• Error Correction Status Module (ECSM)
The resulting 32-bit Power Architecture e200z0h platform represents a reference design, where a single
design description can be configured to generate multiple implementations by including/excluding various
platform modules as required by a specific application.
Throughout this document, several important terms are used to describe the PFLASH2P_LCA module and
its connections. These terms are defined here:
• Port — This is used to describe the AMBA-AHB connection(s) into the PFLASH2P_LCA. This
flash controller supports 2 AHB ports. For these platform designs, the PFLASH2P_LCA p0 port is
always connected to the processor core and the p1 port is connected to the non-core bus masters.
• Bank — This term is used to describe the attached flash memories. From the PFLASH2P_LCA’s
perspective, there may be two or three attached banks of flash memory. There are two “code flash”
arrays required and they are attached to banks 0 and 2. The PFLASH2P_LCA treats banks 0 and 2
in a common manner with various configuration fields of the programming model shared across
the two banks. Additionally, there may be a “data flash” attached to bank1. The PFLASH2P_LCA
interface supports three separate connections, one to each memory bank.
• Array — Within each memory bank, there are one (or more) flash array instantiations. Recall the
maximum capacity of the low-cost array is 512 KB, so devices with larger flash memory bank sizes
require multiple instantiations of the array. Within a bank, the array instantiations are named
array0, array1, etc. Since the PFLASH2P_LCA module supports interface signals for each bank, it
is the responsibility of the SoC design to provide the required address decoding, control generation
and read data muxing when there are multiple arrays within a bank. Regardless of the number of
array instantiations or the number of populated banks, the operating configuration of the
PFLASH2P_LCA is defined by the register values contained in bank0 array0.
• Page — This value defines the number of bits read from the flash array in a single access. For this
controller and memory, the page size is 128 bits (16 bytes).
The nomenclature “page buffers and “line buffers” are used interchangeably.
From an architectural and programming model perspective, there are two “configuration variables”
associated with the PFLASH2P_LCA. These variables define the 2 AHB input ports (p0 and p1) initiating
transactions and the three destination flash memory banks (b0, optional b1, b2). The following
abbreviations for these variables are used throughout the document:
p0 AHB port 0
p1 AHB port 1
b0, bk0 flash memory bank0
b1, bk1 flash memory bank1 (optional)
b2, bk2 flash memory bank2
b02 flash memory banks 0 and 2
Finally since the page buffers and temporary holding registers are associated with both an AHB input port
and a flash bank, they use a bx_py nomenclature. For example, the b0_p0 page buffer refers to the bank0,
port 0 storage elements.
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