NXP Semiconductors MPC5606S - Page 468

e200z0h Core
MPC5606S Microcontroller Reference Manual, Rev. 7
466 Freescale Semiconductor
Figure 14-2. e200z0h SUPERVISOR mode program model SPRs
SPR General
Exception Handling/Control Registers
Save and Restore
Machine State
MSR
PVR
Processor Control Registers
SPRG0
SPRG1
SPR 272
SPR 273
SRR0
SRR1
CSRR0
CSRR1
DSRR0
1
DSRR1
1
SPR 26
SPR 27
SPR 58
SPR 59
SPR 574
SPR 575
Processor ID
PIR
SPR 286
Interrupt Vector Prefix
IVPR SPR 63
Debug Registers
2
Debug Control
DBCR0
DBCR1
DBCR2
DBCR3
1
SPR 308
SPR 309
SPR 310
SPR 561
Instruction Address
Compare
IAC1
IAC2
IAC3
IAC4
SPR 312
SPR 313
SPR 314
SPR 315
Data Address Compare
DAC1
DAC2
SPR 316
SPR 317
1—These e200-specific registers may not be supported
by other PowerPC processors
2—Optional registers defined by the PowerPC Book-E
architecture
3—Read-only registers
Processor Version
Hardware Implementation
Dependent
1
HID0
HID1
SPR 1008
SPR 1009
Cache Registers
SPR 9
General-Purpose
Registers
Count Register
CTR
SPR 8
Link Register
LR
Condition Register
CR
GPR0
GPR1
GPR31
SPR 515
Cache Configuration
(Read-only)
L1CFG0
SPR 1
XER
XER
General Registers
SPR 287
Debug Status
DBSR
SPR 304
System Version
1
SVR
SPR 1023
ESR SPR 62
Exception Syndrome
Data Exception Address
DEAR
SPR 61
Machine Check
Syndrome Register
MCSR
SPR 572
BTB Control
1
SPR 1013
BUCSR
BTB Register
Memory Management Registers
Process ID
PID0 SPR 48
Configuration (read only)
SPR 1015
MMUCFG
DVC1
DVC2
SPR 318
SPR 319