e200z0h Core
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 465
The Power Architecture Book E defines register-to-register operations for all computational instructions.
Source data for these instructions are accessed from the on-chip registers or are provided as immediate
values embedded in the opcode. The three-register instruction format allows specification of a target
register distinct from the two source registers, thus preserving the original data for use by other
instructions. Data is transferred between memory and registers with explicit load and store instructions
only.
Figure 14-2 and Figure 14-3 show the e200 register set including the registers which are accessible while
in supervisor mode, and the registers which are accessible in user mode. The number to the right of the
special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register
(for example, the integer exception register (XER) is SPR 1).
NOTE
e200z0h is a 32-bit implementation of the Power Architecture Book E
specification. In this document, register bits are sometimes numbered from
bit 0 (Most Significant Bit) to 31 (Least Significant Bit), rather than the
Book E numbering scheme of 32:63, thus register bit numbers for some
registers in Book E are 32 higher.
Where appropriate, the Book E defined bit numbers are shown in
parentheses.
To Next Page
Loading...
