FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
680 Freescale Semiconductor
Base + 0x0000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MDIS
FRZ FEN
HALT
NOT
_RDY
0
SOFT
_RST
FRZ
_ACK
SUPV
0
WRN
_EN
LPM
_ACK
0 0
SRX
_DIS
BCC
W
Reset —
1
1
Reset value of this bit is different on various platforms. Consult the specific MCU documentation to determine its
value.
101100—
2
2
Different on various platforms, but it is always the opposite of the MDIS reset value.
100—
3
3
Different on various platforms, but it is always the same as the MDIS reset value.
0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00
LPRIO
_EN
AEN
00
IDAM
00
MAXMB
W
Reset0000000000001111
Figure 18-5. Module Configuration Register (MCR)
Table 18-8. MCR field descriptions
Field Description
MDIS Module Disable
This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down the
clocks to the CAN Protocol Interface and Message Buffer Management submodules. This is the only
bit in MCR not affected by soft reset. See
Section 18.4.9.2, Module Disable mode, for more
information.
0 Enable the FlexCAN module
1 Disable the FlexCAN module
FRZ Freeze Enable
The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR Register is set or when
the MCU is stopped by a debugger. When FRZ is asserted, FlexCAN is enabled to enter Freeze
mode. Negation of this bit field causes FlexCAN to exit from Freeze mode.
0 Not enabled to enter Freeze mode
1 Enabled to enter Freeze mode
FEN FIFO Enable
This bit controls whether the FIFO feature is enabled or not. When FEN is set, MBs 0 to 7 cannot
be used for normal reception and transmission because the corresponding memory region
(0x80–0xFF) is used by the FIFO engine. See Section 18.3.3, Rx FIFO Structure, and
Section 18.4.7, Rx FIFO, for more information.
0 FIFO not enabled
1 FIFO enabled
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