NXP Semiconductors MPC5606S - Page 240

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
238 Freescale Semiconductor
Figure 9-4. eMIOS200 block diagram
1
1.This diagram shows a 24-channel eMIOS200. On MPC5606S, eMIOS200_0 has 16 channels (8–23) and
eMIOS200_1 has 8 channels (16–23). Thus, not all channels shown are available.
Real-time signal
BIU
Counter Buses
(Time bases)
IP Interface
submodules
all
IIB
Interrupt signals
Slave bus signals
Global signals
DMA interface signals
Global Time
Global Time
enhanced Modular Input/Output System
Clock
Prescaler
system clock
internal counter clock enable
................
Output disable control Bus
[A]
CH[0]
EMIOSI[0]
EMIOSO[0]
ipp_obe_emios_ch[0]
see note 1
emios_flag_out[0]
Notes: 1. Connection between UC[n-1] and UC[n]
CH[7]
EMIOSI[7]
EMIOSO[7]
ipp_obe_emios_ch[7]
emios_flag_out[7]
[B]
[A]
CH[8]
EMIOSI[8]
EMIOSO[8]
ipp_obe_emios_ch[8]
emios_flag_out[8]
ch[15]
EMIOSI[15]
EMIOSO[15]
ipp_obe_emios_ch[15]
emios_flag_out[15]
[C]
[A]
CH16]
EMIOSI[16]
EMIOSO[16]
ipp_obe_emios_ch[16]
emios_flag_out[16]
CH[23]
EMIOSI[23]
EMIOSO[23]
ipp_obe_emios_ch[23]
emios_flag_out[23]
[D]
Counter Buses
(Time bases)
................
Counter Buses
(Time bases)
................
necessary to implement QDEC mode
Base Enable Out
Base Enable In
Output Disable
Input[0:3]
Notes: 2: Illustration of a 28 channel eMIOS200