Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
250 Freescale Semiconductor
FCK Filter Clock select bit
The FCK bit selects the clock source for the programmable input filter.
0 Prescaled clock
1 Main clock
FEN FLAG Enable bit
The FEN bit allows the Unified Channel FLAG bit to generate an interrupt signal or a DMA request
signal (the type of signal to be generated is defined by the DMA bit).
0 Disable (FLAG does not generate an interrupt or DMA request)
1 Enable (FLAG will generate an interrupt or DMA request)
FORCMA Force Match A bit
For output modes, the FORCMA bit is equivalent to a successful comparison on comparator A
(except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit
is valid for every output operation mode which uses comparator A; otherwise it has no effect.
0 Has no effect
1 Force a match at comparator A
Note: For input modes, the FORCMA bit is not used and writing to it has no effect.
FORCMB Force Match B bit
For output modes, the FORCMB bit is equivalent to a successful comparison on comparator B
(except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit
is valid for every output operation mode which uses comparator B; otherwise it has no effect.
0 Has no effect
1 Force a match at comparator B
Note: For input modes, the FORCMB bit is not used and writing to it has no effect.
BSL[0:1] Bus Select bits
The BSL[0:1] bits are used to select either one of the counter buses or the internal counter to be used
by the Unified Channel. Refer to
Ta ble 9-19 for details.
EDSEL Edge Selection bit
For input modes, the EDSEL bit selects whether the internal counter is triggered by both edges of a
pulse or only by a single edge, as defined by the EDPOL bit. When not shown in the mode of
operation description, this bit has no effect.
0 Single-edge triggering defined by the EDPOL bit
1 Both edges triggering
For GPIO mode, the EDSEL bit selects whether a FLAG can be generated.
0 A FLAG is generated as defined by the EDPOL bit
1 No FLAG is generated
For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match.
0 The EDPOL value is transferred to the output flip-flop
1 The output flip-flop is toggled
Table 9-15. EMIOSC[n] field descriptions (continued)
Field Description
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