NXP Semiconductors MPC5606S - Page 203

Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 201
8.4.3.1.7 Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)
This register controls the auxiliary clock 1 divider.
Table 8-9. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) field descriptions
Field Description
SELCTL Auxiliary Clock 1 Source Selection Control — This value selects the current source for auxiliary clock 1.
0000 div. 4-16 MHz external oscillator
0001 div. 16 MHz int. RC osc.
0010 Secondary FMPLL
0011 Primary FMPLL
0100 reserved
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
Address 0xC3FE_038C Access: Supervisor read/write, User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DE0
0 0 0
DIV0
0 0 0 0 0 0 0 0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-9. Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)
Table 8-10. Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0) field descriptions
Field Description
DE0 Divider 0 Enable
0 Disable auxiliary clock 1 divider 0.
1 Enable auxiliary clock 1 divider 0.
DIV0 Divider 0 Division Value — The resultant eMIOS0 clock will have a period DIV0 + 1 times that of auxiliary clock 1. If
the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV 0 field is ignored and the eMIOS0 clock remains
disabled.