Reset Generation Module (MC_RGM)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1085
Table 31-9. Functional Event Short Sequence Register (RGM_FESS) field descriptions
Field Description
SS_EXR Short Sequence for External Reset
0 The reset sequence triggered by an external reset event will start from Phase1
1 The reset sequence triggered by an external reset event will start from Phase3, skipping Phase1 and Phase2
SS_FLASH Short Sequence for code or data flash fatal error
0 The reset sequence triggered by a code or data flash fatal error event will start from Phase1
1 The reset sequence triggered by a code or data flash fatal error event will start from Phase3, skipping Phase1
and Phase2
SS_LVD45 Short Sequence for 4.5V low-voltage detected
0 The reset sequence triggered by a 4.5V low-voltage detected event will start from Phase1
1 The reset sequence triggered by a 4.5V low-voltage detected event will start from Phase3, skipping Phase1
and Phase2
SS_CMU0_F
HL
Short Sequence for CMU0 clock frequency higher/lower than reference
0 The reset sequence triggered by a CMU0 clock frequency higher/lower than reference event will start from
Phase1
1 The reset sequence triggered by a CMU0 clock frequency higher/lower than reference event will start from
Phase3, skipping Phase1 and Phase2
SS_CMU0_
OLR
Short Sequence for FXOSC frequency lower than reference
0 The reset sequence triggered by a FXOSC frequency lower than reference event will start from Phase1
1 The reset sequence triggered by a FXOSC frequency lower than reference event will start from Phase3,
skipping Phase1 and Phase2
SS_FMPLL0 Short Sequence for FMPLL0 fail
0 The reset sequence triggered by a FMPLL0 fail event will start from Phase1
1 The reset sequence triggered by a FMPLL0 fail event will start from Phase3, skipping Phase1 and Phase2
SS_CHKST
OP
Short Sequence for checkstop reset
0 The reset sequence triggered by a checkstop reset event will start from Phase1
1 The reset sequence triggered by a checkstop reset event will start from Phase3, skipping Phase1 and Phase2
SS_SOFT Short Sequence for software reset
0 The reset sequence triggered by a software reset event will start from Phase1
1 The reset sequence triggered by a software reset event will start from Phase3, skipping Phase1 and Phase2
SS_CORE Short Sequence for core reset
0 The reset sequence triggered by a core reset event will start from Phase1
1 The reset sequence triggered by a core reset event will start from Phase3, skipping Phase1 and Phase2
SS_JTAG Short Sequence for JTAG initiated reset
0 The reset sequence triggered by a JTAG initiated reset event will start from Phase1
1 The reset sequence triggered by a JTAG initiated reset event will start from Phase3, skipping Phase1 and
Phase2
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