NXP Semiconductors MPC5606S - Page 1114

Sound Generation Logic (SGL)
MPC5606S Microcontroller Reference Manual, Rev. 7
1112 Freescale Semiconductor
4
SDCIE
Sound Duration Complete Interrrupt Enable Bit. Enables or disables the interrupt ipi_int_sgl output
signal.
1 Interrupt ipi_int_sgl is enabled
0 Interrupt ipi_int_sgl is not enabled
12–15
CH2_SEL
PWM channel select (Mux B). Used to select specific PWM channel to be used by Mux B for sound
generation. See Tabl e 34-4 for a detailed description.
16–22
PRE
Clock divider value for the prescaler. See Tabl e 34-5 for a detailed description.
28–31
CH1_SEL
PWM channel select (Mux A). Used to select specific PWM channel to be used by Mux A for sound
generation. See
Table 34-4 for a detailed description.
Table 34-4. eMIOS channel mapping
CHx_SEL eMIOS channel selected CHx_SEL eMIOS channel selected
0x00 eMIOS_0 Channel 16 0x08 eMIOS_1 Channel 16
0x01 eMIOS_0 Channel 17 0x09 eMIOS_1 Channel 17
0x02 eMIOS_0 Channel 18 0x0A eMIOS_1 Channel 18
0x03 eMIOS_0 Channel 19 0x0B eMIOS_1 Channel 19
0x04 eMIOS_0 Channel 20 0x0C eMIOS_1 Channel 20
0x05 eMIOS_0 Channel 21 0x0D eMIOS_1 Channel 21
0x06 eMIOS_0 Channel 22 0x0E eMIOS_1 Channel 22
0x07 eMIOS_0 Channel 23 0x0F eMIOS_1 Channel 23
Table 34-5. Prescaler clock divider
PRE Divide ratio
0000000 1
0000001 2
0000010 3
0000011–1111110 4–127
1111111 128
Table 34-3. MODE_SEL field descriptions (continued)
Field Description