NXP Semiconductors MPC5606S - Page 272

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
270 Freescale Semiconductor
Figure 9-35. OPWMB mode with 0% duty cycle
Figure 9-36 shows the operation of OPWMB mode with the Output Disable signal being asserted. The
Output Disable forces a transition in the output pin to the EDPOL bit value. After deassertion, the Output
Disable allows the output pin to transition at the next A1 or B1 match. Note that the Output Disable does
not modify the FLAG bit behavior. Note that there is one system clock delay between the assertion of the
output disable signal and the transition of the output pin to EDPOL.
1
4
match A1 negative edge detection
8
A1 value
0x000004
A1 match
A1 match negative edge detection
output pin
EDPOL = 0
Selected
TIME
match B1 negative edge detection
B1 match
B1 match negative edge detection
B1 value
0x000008
clock
prescaler
A2 value
0x000000
write to A2
0x000000
A1 match positive edge detection
match A1 positive edge detection
1
cycle n
cycle n+1
8
counter bus
FLAG set event
FLAG pin/register