NXP Semiconductors MPC5606S - Page 271

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 269
Figure 9-34 shows the operation of the OPWMB mode regarding A1 and B1 matches and the transition of
the channel output pin. In this example, EDPOL is set to zero.
Figure 9-34. OPWMB mode matches and flags
Note that the output pin transitions are based on the negative edges of the A1 and B1 match signals.
Figure 9-34 shows in cycle n + 1 the A1 register being set to zero. In this case, the match positive edge is
used instead of the negative edge to transition the output flip-flop.
Figure 9-35 shows the channel operation for 0% duty cycle. Note that the A1 match positive edge signal
occurs at the same time as the B1 = 0x8 negative edge signal. In this case, the A1 match has precedence
over the B1 match, causing the output pin to remain at the EDPOL bit value, thus generating a 0% duty
cycle signal.
1
4
match A1 negative edge detection
6
A1 value 0x000004
A1 match
A1 match negative edge detection
output pin
EDPOL = 0
TIME
match B1 negative edge detection
B1 match
B1 match negative edge detection
B1 value
0x000006
clock
prescaler
A2 value
0x000000
write to A2
0x000000
A1 match positive edge detection
match A1 positive edge detection
1
cycle n
cycle n +1
8
6
FLAG set event
Selected
counter bus
FLAG pin/register