Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606S Microcontroller Reference Manual, Rev. 7
732 Freescale Semiconductor
20.4.3.1 I
2
C Bus Address Register
This register contains the address the I
2
C Bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
20.4.3.2 I
2
C Bus Frequency Divider Register
Offset 0x00000 Access: User read/write
0 1 2 3 4 5 6 7
R
ADR
0
W
Reset 0 0 0 0 0 0 0 0
Figure 20-2. I
2
C Bus Address Register (IBAD)
Table 20-2. IBAD field descriptions
Field Description
ADR Slave Address. Specific slave address to be used by the I
2
C Bus module.
Note: The default mode of I
2
C Bus is Slave mode for an address match on the bus.
Offset 0x0001 Access: User read/write
0 1 2 3 4 5 6 7
R
IBC
W
Reset 0 0 0 0 0 0 0 0
Figure 20-3. I
2
C Bus Frequency Divider Register (IBFD)
Table 20-3. IBFD field descriptions
Field Description
IBC I-Bus Clock Rate. This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider. The IBC bits are decoded to give the Tap and Prescale values as
follows:
0–1 select the prescaled shift register (see Tabl e 20-4)
2–4 select the prescaler divider (see Ta ble 20-5)
5–7 select the shift register tap point (see Table 20-6)
Table 20-4. I-Bus Multiplier Factor
IBC[0:1] MUL
00 01
01 02
10 04
11 RESERVED
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