Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 733
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of Table 20-5. All subsequent tap points are separated by 2
IBC[2:4]
as shown in the
tap2tap column in Table 20-5. The SCL Tap is used to generate the SCL period and the SDA Tap is used
to determine the delay from the falling edge of SCL to the change of state of SDA; that is, the SDA hold
time.
Table 20-5. I-Bus Prescaler Divider Values
IBC[2:4]
scl2start
(clocks)
scl2stop
(clocks)
scl2tap
(clocks)
tap2tap
(clocks)
000 2 7 4 1
001 2 7 4 2
010 2 9 6 4
011 6 9 6 8
100 14 17 14 16
101 30 33 30 32
110 62 65 62 64
111 126 129 126 128
Table 20-6. I-Bus Tap and Prescale Values
IBC[5:7]
SCL Tap
(clocks)
SDA Tap
(clocks)
000 5 1
001 6 1
010 7 2
011 8 2
100 9 3
101 10 3
110 12 4
111 15 4
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