NXP Semiconductors MPC5606S - Page 736

Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606S Microcontroller Reference Manual, Rev. 7
734 Freescale Semiconductor
Figure 20-4. SDA Hold Time
Figure 20-5. SCL Divider and SDA Hold
The equation used to generate the divider values from the IBFD bits is:
SCL Divider = MUL × {2 × (scl2tap + [(SCL_Tap – 1) × tap2tap] + 2)} Eqn. 20-1
The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in
Table 20-7. The equation used to generate the SDA Hold value from the IBFD bits is:
SDA Hold = MUL × {scl2tap + [(SDA_Tap – 1) × tap2tap] + 3} Eqn. 20-2
The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:
SCL Hold(start) = MUL × [scl2start + (SCL_Tap – 1) × tap2tap] Eqn. 20-3
SCL Hold(stop) = MUL × [scl2stop + (SCL_Tap – 1) × tap2tap] Eqn. 20-4
SDA
SCL
SDA Hold
SCL Divider
SDA
SCL
Start condition Stop condition
SCL Hold(start)
SCL Hold(stop)