Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
1028 Freescale Semiconductor
Additional details about the error flags contained in that register can be found in Table 30-50.
RBDF RX Buffer Drain Flag: Will be set if the QSPI_SFMSR[RXNE] status bit is asserted, i.e., the RX Buffer
is not empty.
Refer to Section 30.5.3.5.2, Receive Buffer Drain Interrupt or DMA Request, for details.
Writing a 1 into that bit triggers a RX Buffer POP event. If the RX Buffer is empty writing 1 into that bit
clears the flag.
AHB Buffer Related Flags
ABOF AHB Buffer Overflow Flag: Set when state machine QSPI_IF tried to push data although AHB buffer
was full.
SFM Command Related Flags
IPAEF IP Command Trigger during AHB Access Error Flag. Set when the following condition occurs:
• A write access occurs to the QSPI_ICR register and the QSPI_SFMFR[AHB_ACC] bit is set. Any
command leading to the assertion of the IPAEF flag is ignored
IPIEF IP Command Trigger during IP Access Error Flag. Set on any of the following conditions:
• A write access occurs to the QSPI_ICR register and the QSPI_SFMFR[IP_ACC] bit is set. Any
command leading to the assertion of the IPIEF flag is ignored
• A write access occurs to the QSPI_SFAR register and the QSPI_SFMFR[IP_ACC] bit is set.
ICEF Instruction Code Error Flag: Set when a wrong instruction code is encountered or in case of mode bit
collision
1
. The instruction which led to the assertion of the ICEF flag is not executed.
Wrong commands issued via the AHB interface are not detected.
TFF Transaction Finished Flag: Set when the QuadSPI module has finished a transaction on the external
flash device. If an error occurred or the transaction was terminated the related error flags are valid at
the latest in the same clock cycle when the TFF flag is asserted.
1
Refer to Section 30.4.3.19, Serial Flash Mode Status Register (QSPI_SFMSR), SFMSR[CONTMODE] for
the description of a mode bit collision
Table 30-33. QSPI_SFMFR field descriptions (continued)
Field Description
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