Reset Generation Module (MC_RGM)
MPC5606S Microcontroller Reference Manual, Rev. 7
1088 Freescale Semiconductor
NOTE
JTAG logic has its own independent reset control and is not controlled by
the MC_RGM in any way.
The reset sequence is comprised of five phases managed by a state machine, which ensures that all phases
are correctly processed through waiting for a minimum duration and until all processes that need to occur
during that phase have been completed before proceeding to the next phase.
The state machine used to produce the reset sequence is shown in Figure 31-11.
‘destructive’ resets all except some clock/reset management yes yes
external reset all except some clock/reset management and debug yes yes
‘functional’ resets all except some clock/reset management and debug programmable
1
programmable
2
shortened ‘functional’ resets
3
flip-flops except some clock/reset management programmable
1
programmable
2
1
The assertion of the external reset is controlled via the RGM_FBRE register.
2
The boot mode is captured if the external reset is asserted.
3
The short sequence is enabled via the RGM_FESS register.
Table 31-12. MC_RGM Reset Implications (continued)
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