Stepper Motor Controller (SMC)
MPC5606S Microcontroller Reference Manual, Rev. 7
1130 Freescale Semiconductor
To prevent the output from inconsistent signals, the duty cycle registers are double buffered. The SMC
module will use working registers to generate the output signals. The working registers are copied from
the bus accessible registers at the following conditions:
• MCPER[PER] is set to 0 (all channels are disabled in this case)
• MCCCx[MCAM] of the respective channel is set to 0 (channel is disabled)
• A PWM timer counter overflow occurs while in half H-bridge or full H-bridge mode
• A PWM channel pair is configured to work in Dual Full H-Bridge mode and a PWM timer counter
overflow occurs after the odd
1
duty cycle register of the channel pair has been written.
In this way, the output of the PWM will always be either the old PWM waveform or the new PWM
waveform, not some variation in between.
Reads of this register return the most recent value written. Reads do not necessarily return the value of the
currently active sign, duty cycle, and dither functionality due to the double buffering scheme.
Table 35-8. MCDCx field descriptions
Field Description
SIGN[4] Sign Bit. The SIGN[4] bit is used to define which output will drive the PWM signal in (dual) full-H-bridge
modes. The SIGN[4] bit has no effect in half-bridge modes. See Section 35.4.1.3.2, Sign Bit
(MCDCx[SIGN]) and Table 35-20 for detailed information about the impact of MCCTL1[RECIRC] and
SIGN[4] bit on the PWM output.
SIGN[3:0] Sign Bit Extension. Replicates the SIGN[4] bit towards the DUTY field to make the whole register a
signed representation for the duty cycle length.
DUTY Duty Cycle Length. DUTY defines the number of motor controller timer counter clocks the
corresponding output is driven low (
MCCTL1[RECIRC] = 0) or is driven high (MCCTL1[RECIRC] = 1).
Setting all bits to 0 will give a static high output in case of MCCTL1[RECIRC] = 0; otherwise, a static
low output. Values greater than or equal to the contents of the period register will generate a static low
output in case of
MCCTL1[RECIRC] = 0, or a static high output if MCCTL1[RECIRC] = 1.
1. Odd duty cycle register: MCDCx+1, x = 2n
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