NXP Semiconductors MPC5606S

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System Integration Unit Lite (SIUL)

MPC5606S Microcontroller Reference Manual, Rev. 7

1186 Freescale Semiconductor

Figure 37-1. SIUL block diagram

Up to 105 I/O pins in the 144-pin packages; up to 133 I/O pins in the 176- and 208-pin packages

IPS

BUS

Data

Pad Input

Interrupt

Controller

IPS

Master

- Configuration

- Glitch Filter

Pad Config (IOMUXC)

Pad Cfg (PCRs)

GPIO Functionality

133

MUX

PADS

133

SIUL Module

Interrupt Functionality

Main Page

Default Chapter3
- Table of Contents3
- Introduction43
- MPC5606S Family Comparison45
- Block Diagram47
- Feature Details50
Chapter 153
- E200Z0H Core Processor53
Chapter 1055
Crossbar Switch (XBAR)55
Chapter 15 Enhanced Direct Memory Access (Edma)56
Chapter 2157
Interrupt Controller (INTC)57
- System Integration Unit (SIU)58
- Sram59
  - Enhanced Modular Input/Output System (Emios)60
Chapter 5 Analog-To-Digital Converter (ADC)61
Chapter 11 Deserial Serial Peripheral Interface (DSPI)62
- Flexcan63
Chapter 35 Stepper Motor Controller (SMC)69
- IEEE 1149.1 JTAG Controller (JTAGC)70
- How to Use the MPC5606S Documents71
- Using the MPC5606S73
  - Software Design74
  - Input/Output Pins75
Chapter 277
- Memory Map78
- Memory Map79
- Memory Map80
- Memory Map81
  - Memory Map82
  - Introduction83
Chapter 384
- Package Pinouts84
- Pad Configuration During Reset Phases87
- Pad Types88
- System Pins89
- Functional Ports90
- Signal Details109
Chapter 4121
- Access Errors121
  - Features122
  - External Signal Description123
  - Memory Map124
- SWT Interrupt Register (SWT_IR)125
- SWT Timeout Register (SWT_TO)126
- SWT Window Register (SWT_WN)127
- SWT Counter Output Register (SWT_CO)128
  - Functional Description129
  - Overview131
- Device-Specific Implementation132
  - Functional Description133
  - Normal Conversion Operating Modes134
  - Injected Channel Conversion135
  - Abort Conversion136
- Analog Clock Generator and Conversion Timings137
- Programmable Analog Watchdog139
- DMA Functionality140
- External Decode Signals Delay141
- Register Descriptions142
- Control Logic Registers145
  - Main Status Register (MSR)147
- Interrupt Registers149
  - Channel Pending Registers (CEOCFR[1..2])150
  - Interrupt Mask Register (IMR)151
  - Channel Interrupt Mask Register (CIMR[1..2])152
  - Watchdog Threshold Interrupt Status Register (WTISR)153
  - Watchdog Threshold Interrupt Mask Register (WTIMR)154
- DMA Registers155
  - DMA Channel Select Register (DMAR[1..2])156
- Threshold Registers157
  - Threshold Register (THRHLR[0:3])158
- Conversion Timing Registers CTR[1..2]159
- Mask Registers160
  - Injected Conversion Mask Registers (JCMR[1..2])161
- Delay Registers162
- Data Registers164
  - Overview167
  - Memory Map168
  - Reset Configuration Half Word Source (RCHW)170
- Single-Chip Boot Mode171
Chapter 6172
- Boot and Alternate Boot172
- BAM Software Flow173
- BAM Resources174
- Download and Execute the New Code175
- Download Start Address, VLE Bit and Code Size176
- Download Data177
- Boot from UART178
- Bootstrap with CAN179
  - Protocol180
    - Interrupts181
    - Introduction183
Chapter 23184
- Main Features184
Chapter 7185
- CAN Sampler Sample Registers 0–11185
- Functional Description186
- Enabling/Disabling the CAN Sampler187
- Baud Rate Generation188
Chapter 8189
- Clock Architecture189
- Auxiliary Clocks190
- Clock Gating191
- Clock Generation Module (MC_CGM)192
- FXOSC External Oscillator211
- Register Description212
- Khz OSC Digital Interface213
- Register Description214
- SIRC Digital Interface215
- Clock Monitor Unit (CMU)226
- Device-Specific Information235
Chapter 9236
- Emios Clocking Configuration236
- Unified Channel Block238
- Unified Channel Memory Map243
- Register Description244
- Emios200 Global FLAG Register (EMIOSGFLAG)245
- Emios200 Output Update Disable (EMIOSOUDIS)246
- Emios200 Disable Channel (EMIOSUCDIS)247
- Emios200 UC a Register (Emiosa[N])248
- Emios200 UC B Register (Emiosb[N])249
- Emios200 UC Counter Register (Emioscnt[N])250
- Emios200 UC Status Register (Emioss[N])255
- Functional Description256
- Unified Channel (UC)258
- Slave Ports284
- Signal Names and Descriptions291
- Serial Peripheral Interface (SPI) Configuration312
  - SPI Master Mode313
  - Receive First in First out (RX FIFO) Buffering Mechanism314
- DSPI Baud Rate and Clock Delay Generation315
  - Baud Rate Generator316
- Transfer Formats318
Chapter 12 Register Summary346
- Register Descriptions355
- Control Descriptor L0_2 Register356
- Control Descriptor L0_3 Register357
- Control Descriptor L0_4 Register358
- Control Descriptor L0_5 Register360
- Control Descriptor L0_6 Register361
- Control Descriptor L0_7 Register363
- Control Descriptor Cursor 2 Register (Ctrldesccursor_2)364
- Control Descriptor Cursor 3 Register (Ctrldesccursor_3)365
- DCU Mode Register (DCU_MODE)366
- BGND Register368
- DISP_SIZE Register369
- HSYN_PARA Register370
- SYN_POL Register371
- Threshold Register372
- Interrupt Status Register (INT_STATUS)373
- Interrupt Mask Register (INT_MASK)375
- COLBAR Registers377
- Divide Ratio (DIV_RATIO) Register381
- SIGN_CALC_1 Register382
- SIGN_CALC_2 Register383
- PDI Status Register384
- PDI Status Mask Register385
- Parameter Error Status (PARR_ERR) Register386
- Mask PARR_ERR Status Register389
- THRESHOLD_INP_BUF_1 Register391
- LUMA Component Register392
- Red Chroma Components393
- Blue Chroma Component Register394
- CRC_POS Register395
- Fg0_Bcolor396
- Global Protection Register397
- Soft Lock Bit Register L0398
- Soft Lock Bit Register L1399
- Soft Lock DISP_SIZE Register401
- Soft Lock HSYNC/VSYNC para Register402
- Soft Lock POL Register403
- Soft Lock L1_TRANSP Register404
- Functional Description405
- TFT LCD Panel Configuration406
- DCU Mode Selection and Background Color408
- Layer Configuration and Blending409
  - Control Descriptors412
  - Graphics and Data Format413
  - Alpha and Chroma-Key Blending415
  - 16 Freescale Semiconductor418
  - Transparency Mode and Blending422
  - Luminance Mode425
- Hardware Cursor426
- Clut/Tile RAM428
- Gamma Correction429
- Synchronizing to Panel Frame Rate430
- Error Detection432
- Register Protection433
- List of Protected Registers434
  - CRC Area Description435
  - Features437
  - Programming for Debug Mode438
  - ITU-R BT.656 Sync Information Extraction439
  - PDI Interface Description440
- Glossary450
  - Introduction451
  - Modes of Operation452
  - Register Descriptions453
  - Functional Description456
  - DMA Channels with no Triggering Capability458
- Microarchitecture Summary464
- Block Diagram465
Chapter 14 Integer Unit Features466
- Unimplemented Sprs and Read-Only Sprs469
- DMA Basic Data Flow508
- DMA Performance511
- Initialization/Application Information514
- DMA Programming Errors515
- DMA Arbitration Mode Considerations516
  - Fixed Group Arbitration, Round-Robin Channel Arbitration517
  - Multiple Requests518
- TCD Status520
  - Preemption Status521
- Dynamic Programming522
- Hardware Request Release Timing523
  - Introduction525
  - Register Description526
Chapter 16527
- Processor Core Type (PCT) Register527
- Miscellaneous Wakeup Control Register (MWCR)528
- Miscellaneous Interrupt Register (MIR)529
- Miscellaneous User-Defined Control Register (MUDCR)530
- ECC Registers531
- ECC Status Register (ESR)532
- ECC Error Generation Register (EEGR)534
- Flash ECC Address Register (FEAR)537
- Flash ECC Master Number Register (FEMR)538
- Flash ECC Data Register (FEDR)539
- RAM ECC Address Register (REAR)540
- RAM ECC Master Number Register (REMR)542
- RAM ECC Data Register (REDR)543
- High-Priority Enables544
Chapter 17563
- 17.2.6.3 Non-Volatile Low/MID Address Space Block Locking Register (NVLML563
  - High Address Space Block Locking Register (HBL)565
  - Secondary Low/MID Address Space Block Locking Register (SLL)566
- Low/MID Address Space Block Select Register (LMS)569
- High Address Space Block Select Register (HBS)570
- Address Register (ADR)571
- Bus Interface Unit 0 Register (BIU0)573
- Bus Interface Unit 2 Register (BIU2)574
- User Test 0 Register (UT0)575
- User Test 1 Register (UT1)577
- User Test 2 Register (UT2)578
- User Multiple Input Signature Register 1 (UMISR1)579
- User Multiple Input Signature Register 2 (UMISR2)580
- User Multiple Input Signature Register 4 (UMISR4)581
- Non-Volatile Private Censorship Password 0 Register (NVPWD0)582
- Non-Volatile Private Censorship Password 1 Register (NVPWD1)583
- Non-Volatile System Censoring Information 1 Register (NVSCI1)584
- Non-Volatile User Options Register (NVUSRO)585
- Programming Considerations586
  - Error Correction Code (ECC)594
- User Mode Operation600
Chapter 26635
- Censored Mode635
- Initialization / Application Information665
  - Flash Memory Setting Recommendations666
- Message Buffer Structure676
- Rx FIFO Structure679
- Transmit Process700
- Receive Process701
- Matching Process702
- Data Coherence704
  - Message Buffer Deactivation705
- Rx FIFO706
- CAN Protocol Related Features707
  - Overload Frames708
  - Arbitration and Matching Timing711
- Flexcan Addressing and RAM Size Configurations715
  - Introduction717
  - Features718
Chapter 19 Bypass Mode719
- External Signal Description720
- Instruction Register721
- Boundary Scan Register722
- TAP Controller State Machine723
- E200Z0 Once Controller728
- DMA Application Information752
- Introduction753
Chapter 40755
- Block Diagram755
- Software Vector Mode756
- Stop Mode757
- INTC Module Configuration Register (INTC_MCR)758
- INTC Interrupt Acknowledge Register (INTC_IACKR)760
- INTC End-Of-Interrupt Register (INTC_EOIR)761
- Functional Description764
- Interrupt Request Sources774
  - Peripheral Interrupt Requests775
  - Last-In First-Out (LIFO)776
- Handshaking with Processor777
  - Hardware Vector Mode Handshaking778
- Initialization/Application Information779
  - Software Vector Mode780
- ISR, RTOS, and Task Hierarchy781
- Order of Execution782
- Priority Ceiling Protocol783
  - Software Configurable Interrupt Requests784
  - Scheduling an ISR on Another Processor785
    - Proper Setting of Interrupt Request Priority786
Chapter 22 Information Specific to this Device787
- Introduction788
- Features789
- Modes of Operation790
- Memory Map and Register Definition791
- Interrupts822
- LCD Waveform Examples823
- Fractional Baud Rate Generation833
- Register Map and Reset Values865
- UART Mode869
- Overview883
  - Features885
- External Signal Description886
- Functional Description897
- Access Evaluation—Hit Determination898
- Putting It All Together and AHB Error Terminations899
- Initialization Information900
- Introduction903
Chapter 13905
- Features905
- External Signal Description906
- Memory Map907
  - Register Description914
Chapter 25916
- Mode Control Register (ME_MCTL)916
- Mode Enable Register (ME_ME)917
- Interrupt Status Register (ME_IS)919
- Interrupt Mask Register (ME_IM)920
- Invalid Mode Transition Status Register (ME_IMTS)921
- Debug Mode Transition Status Register (ME_DMTS)922
- Reset Mode Configuration Register (ME_RESET_MC)924
- Test Mode Configuration Register (ME_TEST_MC)925
- DRUN Mode Configuration Register (ME_DRUN_MC)926
- Run0...3 Mode Configuration Registers (ME_RUN0...3_MC)927
- Stop Mode Configuration Register (ME_STOP_MC)928
- Peripheral Status Register 0 (ME_PS0)930
- Peripheral Status Register 1 (ME_PS1)931
- Peripheral Status Register 2 (ME_PS2)932
- Run Peripheral Configuration Registers (ME_RUN_PC0...7)933
- Low-Power Peripheral Configuration Registers (ME_LP_PC0...7)934
- Peripheral Control Registers (ME_PCTL0...143)935
- Mode Details937
  - Test Mode938
  - Run0...3 Modes939
Chapter 36940
- Stop Mode940
- Standby Mode941
- Target Mode Request942
- Peripheral Clocks Disable943
- Processor Low-Power Mode Entry944
- Flash Modules Switch-On945
- Peripheral Clocks Enable946
- Power Domain #2 Switch-Off947
- FMPLL0 Switch-Off948
- Current Mode Update949
- Protection of Mode Configuration Registers951
  - Safe Mode Transition Interrupt953
- Application Example954
- Introduction957
- Features958
  - Modes of Operation959
- Operating Mode960
- Memory Map and Register Description961
  - Port Configuration Register (PCR)962
  - Development Control Register 1, 2 (DC1, DC2)964
  - Development Status Register (DS)967
  - Read/Write Access Control/Status (RWCS)968
  - Read/Write Access Address (RWA)969
  - Watchpoint Trigger Register (WT)970
- Functional Description971
- Enabling Nexus Clients for TAP Access972
- Configuring the NDI for Nexus Messaging973
- Nexus Messaging974
- Introduction975
- Signal Description976
  - Register Descriptions977
  - Current Timer Value (CVAL) Register978
  - Timer Control (TCTRL) Register979
  - Functional Description980
Chapter 29990
- Power Domain #1 Configuration Register (PCU_PCONF1)990
- Power Domain Status Register (PCU_PSTAT)991
- Mode Transitions992
  - Standby Mode Transition993
  - Power Saving for Memories During Standby Mode994
- Preface995
Chapter 30996
- Glossary for Quadspi Module996
- Introduction997
Chapter 39999
- Overview999
- Quadspi Modes of Operation1000
  - Debug Mode (SPI Modes Only)1001
- Detailed Signal Description1002
- Qspi_Io2—Quadspi Data IO_21003
- AMBA Bus Register Memory Map1004
- IP Bus Register Descriptions1005
- Transfer Count Register (QSPI_TCR)1008
- SPI Status Register (QSPI_SPISR)1014
- PUSH TX FIFO Register (QSPI_PUSHR)1017
- POP RX FIFO Register (QSPI_POPR)1018
- Transmit FIFO Registers 0 – 14 (QSPI_TXFR0 – QSPI_TXFR14)1019
- RX FIFO Registers 0 – 14 (QSPI_RXFR0 – QSPI_RXFR14)1020
- Instruction Code Register (QSPI_ICR)1021
- Sampling Register (QSPI_SMPR)1022
- RX Buffer Status Register (QSPI_RBSR)1023
- RX Buffer Data Registers 0–14 (QSPI_RBDR0–QSPI_RBDR14)1024
- TX Buffer Status Register (QSPI_TBSR)1025
- TX Buffer Data Register (QSPI_TBDR)1026
- Serial Flash Mode Status Register (QSPI_SFMSR)1027
- Serial Flash Mode Flag Register (QSPI_SFMFR)1029
- AHB Bus Register Memory Map Descriptions1031
  - AHB Bus Access Considerations1032
  - Modes of Operation1033
- SPI (Serial Peripheral Interface) Modes1034
  - Start and Stop of SPI Transfers1035
  - Master Mode1036
  - Receive First in First out (RX FIFO) Buffering Mechanism1037
  - Baud Rate and Clock Delay Generation1038
  - SPI Transfer Formats1040
  - Continuous Serial Communications Clock1047
  - SPI Mode Interrupt and DMA Requests1048
- SFM (Serial Flash) Mode1049
  - Issuing SFM Commands1050
  - Flash Programming1051
  - Byte Ordering of Serial Flash Data1053
    - Serial Flash Mode Interrupt and DMA Requests1054
    - TX Buffer Operation1055
  - Power Saving Features1056
  - DMA Usage1065
- Serial Flash Devices1066
  - Supported Instruction Codes in Winbond Devices1067
  - Serial Flash Clock Frequency Limitations1069
Chapter 311079
- Functional Event Status Register (RGM_FES)1079
- Destructive Event Status Register (RGM_DES)1080
- Functional Event Reset Disable Register (RGM_FERD)1082
- Destructive Event Reset Disable Register (RGM_DERD)1083
- Functional Event Alternate Request Register (RGM_FEAR)1084
- Destructive Event Alternate Request Register (RGM_DEAR)1085
- Functional Event Short Sequence Register (RGM_FESS)1086
- Standby Reset Sequence Register (RGM_STDBY)1088
- Functional Description1089
- Phase0 Phase1091
- Phase1 Phase1092
- Destructive Resets1093
- Functional Resets1094
- Alternate Event Generation1095
- Overview1097
- Device Specific Information1099
- Debug Support1100
Chapter 321101
- RTC Control Register (RTCC)1101
- RTC Status Register (RTCS)1103
- RTC Counter Register (RTCCNT)1104
- API Functional Description1105
- Introduction1107
- Register Memory Map1108
Chapter 33 Reset Effects on SRAM Accesses1109
- Initialization and Application Information1110
Chapter 341115
- SOUND_DURATION Register1115
- SGL_STATUS Register1116
  - Interrupts1120
  - Introduction1121
- PWM Alignment Modes1122
- Register Description1127
- Motor Controller Control Register 0 (MCCTL0)1128
- Motor Controller Control Register 1 (MCCTL1)1129
- Motor Controller Period Register (MCPER)1130
- Motor Controller Duty Cycle Register (MCDC0..11)1131
- Short-Circuit Detector Timeout Register (MCSDTO)1133
- PWM Duty Cycle1151
- Output Switching Delay1152
- Reset1157
- Stepper Stall Detection Measurement1176
  - Details of the SSD Measurement1177
- Additional Modes of Operation1179
- SSD Startup1180
- Setting of the PRESCALE Register1182
  - Offset Cancellation Considerations1183
- Stepper Motor Transition Considerations1184
Chapter 37 Register Protection1192
- MCU ID Register #2 (MIDR2)1193
- Interrupt Status Flag Register (ISR)1195
- Interrupt Rising-Edge Event Enable Register (IREER)1196
- Interrupt Filter Enable Register (IFER)1197
- GPIO Pad Data Output Registers (GPDO0_3–GPDO132_135)1204
- Parallel GPIO Pad Data out Registers (PGPDO0–PGPDO4)1205
- Parallel GPIO Pad Data in Register (PGPDI0–PGPDI4)1207
- Interrupt Filter Maximum Counter Registers (IFMC0–IFMC15)1209
- Functional Description1210
- External Interrupts1211
Chapter 381217
- System Status Register (STATUS)1217
- Error Configuration1218
- Debug Status Port Register1219
- Password Comparison Registers1220
- STM Count Register (STM_CNT)1225
- STM Channel Control Register (Stm_Ccrn)1226
- STM Channel Compare Register (Stm_Cmpn)1227
- Introduction1229
Chapter 201230
- Block Diagram1230
  - Detailed Signal Descriptions1231
  - Functional Description1232
- VREG Digital Interface1233
- GPIO Power Supply Configuration1234
- Power Domain Organization1235
Chapter 181239
- Overview1239
  - Features1240
  - External Signal Description1241
- Register Description1242
Chapter 411243
- NMI Configuration Register (NCR)1243
- Wakeup/Interrupt Status Flag Register (WISR)1244
- Interrupt Request Enable Register (IRER)1245
- Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER)1246
- Wakeup/Interrupt Pullup Enable Register (WIPUER)1247
- NMI Management1248
- External Wakeups/Interrupts1249
  - External Interrupt Management1250
- On-Chip Wakeups1251
Appendix A1253
- Registers under Protection1254
- Registers under Protection1255
Registers under Protection1256
- Registers under Protection1257
- Registers under Protection1258
Appendix B1259
Register Map1260
- Register Map1261
- Register Map1262
- Register Map1263
- Register Map1264
- Register Map1265
- Register Map1266
- Register Map1267
- Register Map1268
- Register Map1269
- Register Map1270
- Register Map1271
- Register Map1272
- Register Map1273
- Register Map1274
- Register Map1275
- Register Map1276
- Register Map1277
- Register Map1278
- Register Map1279
- Register Map1280
- Register Map1281
- Register Map1282
- Register Map1283
- Register Map1284
- Register Map1285
- Register Map1286
- Register Map1287
- Register Map1288
- Register Map1289
- Register Map1290
- Register Map1291
- Register Map1292
- Register Map1293
- Register Map1294
- Register Map1295
- Register Map1296
- Register Map1297
- Register Map1298
- Register Map1299
- Register Map1300
- Register Map1301
- Register Map1302
- Register Map1303
- Register Map1304
- Register Map1305
- Register Map1306
- Register Map1307
- Register Map1308
- Register Map1309
- Register Map1310
- Register Map1311
- Register Map1312
- Register Map1313
- Register Map1314
- Register Map1315
- Register Map1316
- Register Map1317
- Register Map1318
- Register Map1319
- Register Map1320
- Register Map1321
- Register Map1322
- Register Map1323
- Register Map1324
Appendix C1325
- C.1 Changes between Revisions 6 and 71325
- C.2 Changes between Revisions 5 and 61327
- C.3 Changes between Revisions 4 and 51331
- C.4 Changes between Revisions 3 and 41332
- C.5 Changes between Revisions 2 and 31337
- C.6 Changes between Revisions 1 and 21340
- C.7 Changes between Revisions 0 and 11344

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