NXP Semiconductors MPC5606S - Page 1202

System Integration Unit Lite (SIUL)
MPC5606S Microcontroller Reference Manual, Rev. 7
1200 Freescale Semiconductor
PSMI[23] 0x517 EMIOS0_CH16 0: PCR[7]
1: PCR[27]
2: PCR[80]
PSMI[24] 0x518 EMIOS0_CH17 0: PCR[5]
1: PCR[122]
PSMI[25] 0x519 EMIOS0_CH18 0: PCR[4]
1: PCR[121]
PSMI[26] 0x51A EMIOS0_CH19 0: PCR[3]
1: PCR[120]
PSMI[27] 0x51B EMIOS0_CH20 0: PCR[2]
1: PCR[119]
PSMI[28] 0x51C EMIOS0_CH21 0: PCR[1]
1: PCR[71]
2: PCR[112]
PSMI[29] 0x51D EMIOS0_CH22 0: PCR[0]
1: PCR[70]
2: PCR[111]
PSMI[30] 0x51E EMIOS0_CH23 0: PCR[26]
1: PCR[98]
PSMI[31] 0x51F EMIOS1_CH16 0: PCR[53]
1: PCR[82]
2: PCR[103]
PSMI[32] 0x520 EMIOS1_CH17 0: PCR[52]
1: PCR[90]
2: PCR[117]
PSMI[33] 0x521 EMIOS1_CH18 0: PCR[9]
1: PCR[29]
2: PCR[51]
PSMI[34] 0x522 EMIOS1_CH19 0: PCR[28]
1: PCR[50]
2: PCR[88]
PSMI[35] 0x523 EMIOS1_CH20 0: PCR[10]
1: PCR[25]
2: PCR[49]
3: PCR[118]
PSMI[36] 0x524 EMIOS1_CH21 0: PCR[24]
1: PCR[48]
2: PCR[89]
PSMI[37] 0x525 EMIOS1_CH22 0: PCR[23]
1: PCR[47]
PSMI[38] 0x526 EMIOS1_CH23 0: PCR[8]
1: PCR[46]
2: PCR[81]
Table 37-12. Peripheral input pin selection (continued)
PSMI register SIUL address offset Peripheral input
Mapping of input pin to
peripheral input
1