Revision History
MPC5606S Microcontroller Reference Manual, Rev. 7
1336 Freescale Semiconductor
Memory Map Added the following footnote to the “Region” section:
“The contents of memory addresses marked as reserved and individual bits within a
memory address that are marked as reserved may return any value when read unless
otherwise indicated.”
Signal Description Renamed the analog pins (were AN..., are ANS...).
Added a column for the 208-pin package to the “System pin descriptions” table.
Corrected all values in the “Debug pin descriptions” table.
Updated the “Port pin summary” table.
Added new information on pad types (including splitting up the existing M pads into two
categories, M1 and M2).
In the “Signal details” table:
• Added “ANS[0:15] connect to ATD channels [32:47]” to the ANS signal description.
• Added “The available 8 multiplexed channels connect to ATD channels [64:71]” to the
MA signal description.
• Deleted “when high; otherwise low to allow a subframe display for pixels” from the
DCU_DE description.
• Changed the descriptions for DCU_TAG, PDI_PCLK, TXD_A, and SSD signals.
• Added QuadSPI signals.
• Deleted “For valid Pixel Data this is high, otherwise low” from the PDI_DE description.
Clock Description Updated register access information in the memory map and register descriptions.
Changed some clock and signal names for consistency.
Revised the system clock generation figure.
In the “Peripheral clock generation registers” table, deleted “CGM_AC0_DC0” from the
DCU entry.
Corrections throughout the Clock Generation Module (MC_CGM) section.
Changed the CR[en_pll_sw] field description.
Revised the “Progressive clock switching” section.
Changed the title of “CMU block diagram” to “CMU component interaction” and, in that
figure, changed “4–40 MHz” to “4–16 MHz”.
Mode Entry Module Corrections throughout chapter.
Updated register access information in the memory map and register descriptions.
Changed some clock and signal names for consistency.
Boot Assist Module Changed some clock and signal names for consistency.
Power Control Unit Removed the trailing “0” from the HALT, STOP, and STANDBY modes.
Updated register access information in the memory map and register descriptions.
Reset Generation
Module
Updated register access information in the memory map and register descriptions.
Changed the RGM_FBRE section to indicate that bits 12 and 13 are reserved.
DMA Channel Mux Changed the bit order for the channel configuration registers.
Flash Memory Changed the delivery value of the NVPWD0 and NVPWD1 registers (was 0xXXXXXXXX,
is 0xFFFFFFFF).
Revised the NVSCI0 and NVSCI1 field descriptions.
Internal Static RAM Added clarifying information about standby modes to the “Low Power Configuration” table.
Interrupt Controller Changed some clock and signal names for consistency.
In the interrupt vector table, renamed the resources for IRQs 193–198 and 201–206.
Table C-5. Changes between revisions 2 and 3 (continued)
Chapter Description
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