EasyManua.ls Logo

NXP Semiconductors MPC5606S - Page 410

NXP Semiconductors MPC5606S
1344 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
408 Freescale Semiconductor
Figure 12-57. Pixel blending stack
The blending algorithm used for each color component is shown in Equation 12-3.
This priority concept is illustrated in Figure 12-58 and Figure 12-59. In this case, there are five layers
enabled, and each contains a graphic that is a solid rectangular block of a single color. The size and shape
of each layer is different. The background color of the panel is set to grey and layers have been placed such
that they overlap each other.
Figure 12-58 shows the individual source graphics and the case where no layer has any blending enabled.
Here, the highest priority layer (in this case layer 0) is fully visible. Layer 1 is visible where layer 0 does
not overlap it. Layer 2 is visible where layer 1 does not overlap it. Layer 3 is overlapped by layers 0 and 1
and so is only partially visible. Layer 4 is partially obscured by all of the other layers. Note that layer 4 is
higher priority than the background color.
Blend1
Blend2
Blend3
Highest priority pixel
Next higher priority pixel
Higher priority pixel
Lowest priority pixel
Two-plane Blending Result
Three-plane blending result
Four-plane blending
Note: All blend stages use the blending settings
defined for the upper pixel.

Table of Contents

Related product manuals