NXP Semiconductors MPC5606S - Page 49

Overview
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 47
• Sound generation and playback utilizing PWM channels and eDMA; supports monotonic and
polyphonic sound
• 24 eMIOS channels providing up to 16 PWM and 24 input capture / output compare channels
• 10-bit Analog-to-Digital Converter (ADC)
— Maximum conversion time of 1 s
— Up to 16 internal channels, expandable to 23 via external multiplexing
• Up to 2 Deserial Serial Peripheral Interface (DSPI) modules for full-duplex, synchronous
communications with external devices (extendable to include up to 8 multiplexed external
channels)
• QuadSPI serial flash memory controller supporting single, dual, and quad modes of operation to
interface to external serial flash memory; QuadSPI can be configured to function as another DSPI
module (MPC5606S only)
• 2 Local Interconnect Network Flexible (LINFlex) controller modules capable of autonomous
message handling (master), autonomous header handling (slave mode), and UART support;
compliant with LIN protocol rev 2.1
• 2 full CAN 2.0B controllers with 64 configurable buffers each; bit rate programmable up to
1 Mbit/s
• Up to 4 Inter-integrated circuit (I
2
C) internal bus controllers with master/slave bus interface
• Up to 133 configurable general purpose pins supporting input and output operations
• Real Time Counter (RTC) with multiple clock sources:
— 128 kHz slow internal RC oscillator or 16 MHz fast internal RC oscillator supporting
autonomous wakeup with 1 ms resolution with maximum timeout of 2 seconds
— 32 kHz slow external crystal oscillator, supporting wakeup with 1 s resolution and maximum
timeout of one hour
— 4–16 MHz fast external crystal oscillator
• System timers:
— 4-channel 32-bit System Timer Module (STM)—included in processor platform
— 4-channel 32-bit Periodic Interrupt Timer (PIT) module
— Software Watchdog Timer (SWT)
• System Integration Unit (SIU) module to manage resets, external interrupts, GPIO, and pad control
• System Status and Configuration Module (SSCM) to provide information for identification of the
device, last boot mode, or debug status, and provides an entry point for the censorship password
mechanism
• Clock Generation Module (MC_CGM) to generate system clock sources and provide a unified
register interface, enabling access to all clock sources
• Clock Monitor Unit (CMU) to monitor the integrity of the main crystal oscillator and the PLL and
act as a frequency meter, measuring the frequency of one clock source and comparing it to a
reference clock