Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
590 Freescale Semiconductor
Example 17-5. Array Integrity check of sectors B0F1 and B0F2.
UT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */
LMS = 0x00000006; /* Set LSL2-1 in LMS: Select Sectors */
UT0 = 0x80000002; /* Set AIE in UT0: Operation Start */
do /* Loop to wait for AID=1 */
{ tmp = UT0; /* Read UT0 */
} while ( !(tmp & 0x00000001) );
data0 = UMISR0; /* Read UMISR0 content*/
data1 = UMISR1; /* Read UMISR1 content*/
data2 = UMISR2; /* Read UMISR2 content*/
data3 = UMISR3; /* Read UMISR3 content*/
data4 = UMISR4; /* Read UMISR4 content*/
UT0 = 0x00000000; /* Reset UTE and AIE in UT0: Operation End */
Margin read
Margin read procedure (either Margin 0 or Margin 1), can be run on unlocked blocks in order to unbalance
the Sense Amplifiers, respect to standard read conditions, so that all the read accesses reduce the margin
vs. 0 (UT0.MRV = 0) or vs. 1 (UT0.MRV = 1). Locked sectors are ignored by MISR calculation and ECC
flagging. The results of the margin reads can be checked comparing checksum value in UMISR0-4.
Since Margin reads are done at voltages that differ than the normal read voltage, lifetime expectancy of
the flash memory macrocell is impacted by the execution of Margin reads.
Doing Margin reads repetitively results in degradation of the flash memory array, and shorten expected
lifetime experienced at normal read levels.
For these reasons the margin read usage is allowed only in Factory mode, while it is forbidden to use it
inside the user application.
In any case the charge losses detected through the Margin mode cannot be considered failures of the device
and no failure analysis will be opened on them.
The Margin Read Setup operation consists of the following sequence of events:
1. Set UTE in UT0 by writing the related password in UT0.
2. Select the block(s) to be checked by writing 1’s to the appropriate register(s) in LMS or HBS
registers.
Note that Lock and Select are independent. If a block is selected and locked, no Array Integrity
Check will occur.
3. Set eventually UT0.AIS bit for a sequential addressing only.
4. Change the value in the UT0.MRE bit from 0 to 1.
5. Select the Margin level: UT0.MRV=0 for 0’s margin, UT0.MRV=1 for 1’s margin.
6. Write a logic 1 to the UT0.AIE bit to start the Margin Read Setup or skip to step 6 to terminate.
7. Wait until the UT0.AID bit goes high.
8. Compare UMISR0-4 content with the expected result.
9. Write a logic 0 to the UT0.AIE, UT0.MRE and UT0.MRV bits.
10. If more blocks are to be checked, return to step 2.
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