Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 615
9:28 AD22-3: ADdress 22-3 (Read Only)
The Address Register provides the first failing address in the event of ECC error (MCR.EER set) or the
first failing address in the event of RWW error (MCR.RWE set), or the address of a failure that may have
occurred in a FPEC operation (MCR.PEG cleared). The Address Register provides also the first address
at which a ECC single error correction occurs (MCR.EDC set), if the SoC is configured to show this
feature.
The ECC double error detection takes the highest priority, followed by the RWW error, the FPEC error and
the ECC single error correction. When accessed ADR will provide the address related to the first event
occurred with the highest priority. The priorities between these 4 possible events is summarized in the
following table.
This address is always a Double Word address that selects 64 bits.
In case of a simultaneous ECC Double Error Detection on both Double Words of the same page, bit AD3
will output 0. The same is valid for a simultaneous ECC Single Error Correction on both Double Words of
the same page.
In User mode, the Address Register is read-only.
Note: An erroneous update of the Address register (ADR) occurs whenever there is a sequence of three
or more events affecting the ADR (ECC single or double bit errors or RWW error) and both the
following conditions apply:
— The priorities are ordered in such a way that only the first event should update ADR.
— The last event, although it does not update ADR, sets the Read While Write Event Error (RWE)
bit or the ECC Data Correction (EDC) bit in the Module Configuration Register (MCR).
For this case, the ADR is wrongly updated with the address related to one of the intervening events.
Example: If a sequence of two double-bit ECC errors is followed by a single-bit correction without
clearing the ECC Event Error flag (EER) in the MCR, then the value found in ADR after the single-bit
correction event is the one related to the second double-bit error (instead of the first one, as
specified).
29:31 Reserved (Read Only).
Write these bits has no effect and read these bits always outputs 0.
Table 17-50. ADR content: priority list
Priority Level Error Flag ADR content
1 MCR.EER = 1 Address of first ECC Double Error
2 MCR.RWE = 1 Address of first RWW Error
3 MCR.PEG = 0 Address of first FPEC Error
4 MCR.EDC = 1 Address of first ECC Single Error Correction
Table 17-49. ADR field descriptions (continued)
Field Description
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