Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 637
— Each AHB input port provides configurable and independent read buffering and page prefetch
support for banks 0 and 2
— Each AHB input port includes four page read buffers (each 128 bits wide) and a prefetch
controller to support single-cycle read responses (zero AHB data phase wait-states) for hits in
the buffers. The buffers implement a least-recently-used replacement algorithm to maximize
performance.
— Each AHB input port interfaces to the optional data flash (bank1) includes a 128-bit register to
temporarily hold a single flash page. This logic supports single-cycle read responses (zero
AHB data phase wait-states) for accesses that hit in the holding register. There is no support for
prefetching associated with this bank.
• Programmable response for read-while-write sequences including support for stall-while-write,
optional stall notification interrupt, optional flash operation abort, and optional abort notification
interrupt
• Separate and independent configurable access timing (common settings for banks 0 and 2, separate
settings for bank1) to support use across a wide range of platforms and frequencies
• Support of address-based read access timing for emulation of other memory types
• Support for reporting of single- and multi-bit flash ECC events
• Typical operating configuration loaded into programming model by system reset
Figure 17-43 shows a simplified block diagram of the PFLASH2P_LCA memory controller.
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