Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 645
B02_P1_PFLM Bank0+2, Port 1 Prefetch Limit. This field controls the prefetch algorithm used by the PFLASH
controller. This field defines the prefetch behavior. In all situations when enabled, only a single
prefetch is initiated on each buffer miss or hit. This field is set to 2b01 by hardware reset.
00 No prefetching is performed.
01 The referenced line is prefetched on a buffer miss, that is, prefetch on miss.
1- The referenced line is prefetched on a buffer miss, or the next sequential page is prefetched on
a buffer hit (if not already present), that is, prefetch on miss or hit.
B02_P1_BFE Bank0+2, Port 1 Buffer Enable. This bit enables or disables page buffer read hits. It is also used to
invalidate the buffers. This bit is set by hardware reset, enabling the page buffers.
0 The page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared.
1 The page buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when
the buffers are successfully filled.
B02_P0_BCFG Bank0+2, Port 0 Page Buffer Configuration. This field controls the configuration of the four page
buffers in the PFLASH controller. The buffers can be organized as a “pool” of available resources,
or with a fixed partition between instruction and data buffers.
If enabled, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the
group and the just-fetched entry then marked as most-recently-used. If the flash access is for the
next-sequential line, the buffer is not marked as most-recently-used until the given address
produces a buffer hit.
00 All four buffers are available for any flash access, that is, there is no partitioning of the buffers
based on the access type.
01 Reserved
10 The buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches
and buffers 2 and 3 for data accesses.
11 The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches
and buffer 3 for data accesses.
This field is set to 2b11 by hardware reset.
B02_P0_DPFE Bank0+2, Port 0 Data Prefetch Enable. This field enables or disables prefetching initiated by a data
read access. This field is cleared by hardware reset.
0 No prefetching is triggered by a data read access
1 If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any data read access
B02_P0_IPFE Bank0+2, Port 0 Instruction Prefetch Enable. This field enables or disables prefetching initiated by
an instruction fetch read access. This field is set by hardware reset.
0 No prefetching is triggered by an instruction fetch read access
1 If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any instruction fetch
read access
B02_P0_PFLM Bank0+2, Port 0 Prefetch Limit. This field controls the prefetch algorithm used by the PFLASH
controller. This field defines the prefetch behavior. In all situations when enabled, only a single
prefetch is initiated on each buffer miss or hit. This field is set to 2b10 by hardware reset.
00 No prefetching is performed.
01 The referenced line is prefetched on a buffer miss, that is, prefetch on miss.
1- The referenced line is prefetched on a buffer miss, or the next sequential page is prefetched on
a buffer hit (if not already present), that is, prefetch on miss or hit.
B02_P0_BFE Bank0+2, Port 0 Buffer Enable. This bit enables or disables page buffer read hits. It is also used to
invalidate the buffers. This bit is set by hardware reset.
0 The page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared.
1 The page buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when
the buffers are successfully filled.
Table 17-64. PFLASH Configuration Register 0 field descriptions (continued)
Field Description
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