NXP Semiconductors MPC5606S - Page 765

Interrupt Controller (INTC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 763
NOTE
The INTC has no spurious vector support. Therefore, if an asserted
peripheral or software settable interrupt request, whose PRIn value in
INTC_PSR0_3–INTC_PSR204_206 is higher than the PRI value in
INTC_CPR, negates before the interrupt request to the processor for that
peripheral or software settable interrupt request is acknowledged, the
interrupt request to the processor still can assert or will remain asserted for
that peripheral or software settable interrupt request. In this case, the
interrupt vector will correspond to that peripheral or software settable
interrupt request. Also, the PRI value in the INTC_CPR will be updated
with the corresponding PRIn value in INTC_PSRn. Furthermore, clearing
the peripheral interrupt request’s enable bit in the peripheral or,
alternatively, setting its mask bit has the same consequences as clearing its
flag bit. Setting its enable bit or clearing its mask bit while its flag bit is
asserted has the same effect on the INTC as an interrupt event setting the
flag bit.
Table 21-10. Interrupt vector table
IRQ # Offset
Size
[Byte]
This Device
Resource Module
Section A (Core Section)
- 0x0000 16 X Critical Input
(INTC software vector mode)
Core
- 0x0010 16 X Machine check / NMI Core
- 0x0020 16 X Data Storage Core
- 0x0030 16 X Instruction Storage Core
- 0x0040 16 X External Input
(INTC software vector mode)
Core
- 0x0050 16 X Alignment Core
- 0x0060 16 X Program Core
- 0x0070 16 X Reserved Core
- 0x0080 16 X System call Core
- 0x0090 96 X Unused Core
- 0x00F0 16 X Debug Core
- 0x0100 1792 X Unused Core
Section B (On-Platform Peripherals)