NXP Semiconductors MPC5606S - Page 894

Memory Protection Unit (MPU)
MPC5606S Microcontroller Reference Manual, Rev. 7
892 Freescale Semiconductor
24.2.2.4.4 MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3)
The fourth word of the MPU region descriptor contains the optional process identifier and mask, plus the
region descriptor’s valid bit.
Since the region descriptor is a 128-bit entity, there are potential coherency issues as this structure is being
updated since multiple writes are required to update the entire descriptor. Accordingly, the MPU hardware
assists in the operation of the descriptor valid bit to prevent incoherent region descriptors from generating
spurious access errors. In particular, it is expected that a complete update of a region descriptor is typically
done with sequential writes to MPU_RGDn.Word0, then MPU_RGDn.Word1,... and finally
MPU_RGDn.Word3. The MPU hardware automatically clears the valid bit on any writes to words {0,1,2}
of the descriptor. Writes to this word set/clear the valid bit in a normal manner.
Since it is also expected that system software may adjust only the access controls within a region descriptor
(MPU_RGDn.Word2) as different tasks execute, an alternate programming view of this 32-bit entity is
provided. If only the access controls are being updated, this operation should be performed by writing to
MPU_RGDAACn (Alternate Access Control n) as stores to these locations do not affect the descriptor’s
valid bit.
27–28
M0SM
Bus master 0 supervisor mode access control. This 2-bit field defines the access controls for bus master
0 when operating in supervisor mode. The M0SM field is defined as:
0b00 r, w, x = read, write and execute allowed
0b01 r, –, x = read and execute allowed, but no write
0b10 r, w, – = read and write allowed, but no execute
0b11 Same access controls as that defined by M0UM for user mode
29–31
M0UM
Bus master 0 user mode access control. This 3-bit field defines the access controls for bus master 0
when operating in user mode. The M0UM field consists of three independent bits, enabling read, write
and execute permissions: {r,w,x}. If set, the bit allows the given access type to occur; if cleared, an
attempted access of that mode may be terminated with an access error (if not allowed by any other
descriptor) and the access not performed.
Offset MPU_Base + 0x400 + (16*n) + 0xc (MPU_RGDn.Word3) Access:Read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PID PIDMASK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V
L
D
W
Reset - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 24-8. MPU Region Descriptor, Word 3 Register (MPU_RGDn.Word3)
Table 24-7. MPU_RGDn.Word2 field descriptions
Field Description