Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1041
Figure 30-28. QuadSPI Transfer Timing Diagram (MTFE=0, CPHA=1, FMSZ=8)
The master initiates the transfer by asserting the PCS signal to the slave. After the t
CSC
delay has elapsed,
the master generates the first SCK edge and at the same time places valid data on the master SO pin. The
slave responds to the first SCK edge by placing its first data bit on its slave SO pin.
At the second edge of the SCK the master and slave sample their SI pins. For the rest of the frame the
master and the slave change the data on their SO pins on the odd-numbered clock edges and sample their
SI pins on the even-numbered clock edges. After the last clock edge occurs a delay of
t
ASC
is inserted before
the master negates the PCS signal. A delay of t
DT
is inserted before a new frame transfer can be initiated
by the master.
30.5.2.8.3 Modified SPI Transfer Format (MTFE = 1, CPHA = 0)
In this Modified Transfer Format both the Master and the Slave sample later in the SCK period than in the
classical modes to allow for delays in device pads and board traces. These delays become a more
significant fraction of the SCK period as the SCK period decreases with increasing baud rates.
The Master and the Slave places data on the SO pins at the assertion of the PCS signal. After the PCS to
SCK delay has elapsed the first SCK edge is generated. The Slave samples the Master SO signal on every
odd numbered SCK edge. The Slave also places new data on the Slave SO on every odd numbered clock
edge.
t
CSC
t
DT
SCK
SCK
MSB first (LSBFE = 0):
LSB first (LSBFE = 1):
MSB
LSB
LSB
MSB
Bit 5
Bit 2
Bit 6
Bit 1
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
t
CSC
= PCS to SCK delay
t
DT
= Delay after Transfer (minimum CS negation time)
(CPOL = 0)
(CPOL = 1)
t
ASC
Master SO/
Master SI/
Slave SI
Slave SO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PCSx/SS
Master and Slave
Sample
t
ASC
= After SCK delay
To Next Page
Loading...
