Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
1042 Freescale Semiconductor
The Master places its second data bit on the SO line one system clock after odd numbered SCK edge. The
point where the Master samples the Slave SO is selected by writing to the SMPL_PT field in the
QSPI_MCR. The SMPL_PT field description in Table 30-9 lists the number of system clock cycles
between the active edge of SCK and the Master Sample point. The Master sample point can be delayed by
one or two system clock cycles.
Figure 30-29 shows the modified transfer format for CPHA = 0. Only the condition where CPOL = 0 is
illustrated. The delayed Master sample points are indicated with a lighter shaded arrow.
Figure 30-29. QuadSPI Modified Transfer Format (MTFE=1, CPHA=0, Fsck = Fsys/4)
30.5.2.8.4 Modified SPI Transfer Format (MTFE = 1, CPHA = 1)
Figure 30-30 shows the Modified Transfer Format for CPHA = 1. Only the condition where CPOL = 0 is
described. At the start of a transfer the QuadSPI asserts the PCS signal to the slave device. After the PCS
to SCK delay has elapsed the master and the slave put data on their SO pins at the first edge of SCK. The
Slave samples the Master SO signal on the even numbered edges of SCK. The Master samples the Slave
SO signal on the odd numbered SCK edges starting with the third SCK edge. The Slave samples the last
bit on the last edge of the SCK. The Master samples the last Slave SO bit one half SCK cycle after the last
edge of SCK. No clock edge will be visible on the Master SCK pin during the sampling of the last bit. The
SCK to PCS delay must be greater or equal to half of the SCK period.
t
CSC
SCK
System
Master
Slave
PCS
t
CSC
= PCS to SCK delay
SO
Master
SO
Sample
Slave
Sample
Sys
1 2 3 4 5 6
Clock
t
ASC
Clk
Sys
Clk
t
ASC
= After SCK delay
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