NXP Semiconductors MPC5606S - Page 1070

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
1068 Freescale Semiconductor
Note also that the serial flash device clock SCK is inverted w.r.t. the
QuadSPI internal reference clock.
Figure 30-37. Serial Flash Sampling Clock Timing
The rising edge of the internal reference clock is taken as timing reference for the data output of the serial
flash. After a time of t
Del,total
the data arrive at the internal sampling stage of the QuadSPI module.
According to Figure 30-36 the following parts of the delay chain contribute to t
Del,total
:
1. Output delay of the serial flash clock output of the device containing the QuadSPI module
2. Wire delay of application/PCB from the device containing the QuadSPI module to the external
serial flash device
3. Clock to data out delay of the external serial flash device, including input and output delays
4. Wire delay of application/PCB from the external serial flash device to the device containing the
QuadSPI module
5. Input delay belonging to the data in input
The possible points in time for the sampling of the incoming data are denoted as N/1, I/1, N/2 and I/2
above. The sampling point relevant for the internal sampling is configured in the QSPI_SMPR register,
refer to
Section 30.4.3.13, Sampling Register (QSPI_SMPR), for details. Note that the falling edges of the
reference clock are not actually used, instead the inverted clock is used for sampling at these positions.
Table 30-54 below gives an overview of the available configurations for the commands running at regular
(full) speed:
internal ref clock
serial flash data
internal reference for serial flash data sampling
t
Del,total
N/1 N/2
I/1 I/2
Possible Sampling Points
SCK—serial flash clock