Stepper Motor Controller (SMC)
MPC5606S Microcontroller Reference Manual, Rev. 7
1136 Freescale Semiconductor
• Dual full H-bridge mode can be used to control either a stepper motor or a 360 air core instrument.
In this case two PWM channels are combined.
• In full H-bridge mode, each PWM channel is updated independently.
• In half H-bridge mode, one pin of the PWM channel can generate a PWM signal to control a 90
air core instrument (or other load requiring a PWM signal) and the other pin is unused.
The mode of operation for PWM channel x is determined by the output mode bits MCCCx[MCOM]. After
a reset occurs, each PWM channel will be disabled, the corresponding pins are released.
Each PWM channel consists of two pins. One output pin will generate a PWM signal. The other will
operate as logic high or low output depending on the state of the recirculation bit MCCTL1[RECIRC]
(refer to Section 35.4.1.3.3, Recirculation Bit (MCCTL1[RECIRC])), while in (dual) full H-bridge mode,
or will be released, while in half H-bridge mode. The state of the sign bit MCDCx[SIGN[4]] in the duty
cycle register determines the pin where the PWM signal is driven in full H-bridge mode. While in half
H-bridge mode, the state of the released pin is determined by other modules associated with this pin.
Associated with each PWM channel pair n are two PWM channels, x and x + 1, where x = 2 * n and n
(0,1,2... 5) is the PWM channel pair number. Duty cycle register x controls the sign of the PWM signal
(which pin drives the PWM signal) and the duty cycle of the PWM signal for SMC channel x. The pins
associated with PWM channel x are MnC0P and MnC0M. Similarly, duty cycle register x + 1 controls the
sign of the PWM signal and the duty cycle of the PWM signal for channel x + 1. The pins associated with
PWM channel x + 1 are MnC1P and MnC1M. This is summarized in Table 35-19.
Table 35-19. Corresponding Registers and Pin Names for each PWM Channel Pair
PWM Channel
Pair Number
PWM
Channel
Control
Register
Duty Cycle Register Channel Number Pin
Names
n
MCCCx MCDCx
PWM Channel x, x = 2n
MnC0M
MnC0P
MCCCx+1 MCDCx+1
PWM Channel x+1, x = 2n
MnC1M
MnC1P
0
MCCC0 MCDC0 PWM Channel 0
M0C0M
M0C0P
MCCC1 MCDC1 PWM Channel 1
M0C1M
M0C1P
1
MCCC2 MCDC2 PWM Channel 2
M1C0M
M1C0P
MCCC3 MCDC3 PWM Channel 3
M1C1M
M1C1P
2
MCCC4 MCDC4 PWM Channel 4
M2C0M
M2C0P
MCCC5 MCDC5 PWM Channel 5
M2C1M
M2C1P
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