Stepper Motor Controller (SMC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1137
35.4.1.1.1 Dual full H-bridge mode
PWM channel pairs x and x + 1 operate in dual full H-bridge mode if both channels are enabled
(MCCCx[MCAM]=0x1, 0x2, or 0x3) and the output mode bits MCCCx[MCOM] in both PWM channel
control registers are set to 0x3.
A typical configuration in dual full H-bridge mode is shown in Figure 35-17. PWM channel x drives the
PWM output signal on either MnC0P or MnC0M. If MnC0P drives the PWM signal, MnC0M will be
output either high or low depending on the MCCTL1[RECIRC] bit. If MnC0M drives the PWM signal,
MnC0P will be an output high or low. PWM channel x + 1 drives the PWM output signal on either MnC1P
or MnC1M. If MnC1P drives the PWM signal, MnC1M will be an output high or low. If MnC1M drives
the PWM signal, MnC1P will be an output high or low. This results in motor recirculation currents on the
high side drivers (MCCTL1[RECIRC] = 0) while the PWM signal is at a logic high level, or motor
recirculation currents on the low side drivers (MCCTL1[RECIRC] = 1) while the PWM signal is at a logic
low level. The pin driving the PWM signal is determined by the sign bit MCDCx[SIGN[4]] for the
corresponding channel and the state of the MCCTL1[RECIRC] bit. The value of the PWM duty cycle is
determined by the value of the duty cycle bits MCDCx[DUTY] for the corresponding channel.
3
MCCC6 MCDC6 PWM Channel 6
M3C0M
M3C0P
MCCC7 MCDC7 PWM Channel 7
M3C1M
M3C1P
4
MCCC8 MCDC8 PWM Channel 8
M4C0M
M4C0P
MCCC9 MCDC9 PWM Channel 9
M4C1M
M4C1P
5
MCCC10 MCDC10 PWM Channel 10
M5C0M
M5C0P
MCCC11 MCDC11 PWM Channel 11
M5C1M
M5C1P
Table 35-19. Corresponding Registers and Pin Names for each PWM Channel Pair (continued)
PWM Channel
Pair Number
PWM
Channel
Control
Register
Duty Cycle Register Channel Number Pin
Names
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