NXP Semiconductors MPC5606S - Page 1200

System Integration Unit Lite (SIUL)
MPC5606S Microcontroller Reference Manual, Rev. 7
1198 Freescale Semiconductor
37.5.3.9 Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI40_42)
Via routing it is possible to define different pads to be possible inputs for a certain peripheral function.
In order to multiplex different pads to the same peripheral input, the SIUL provides a register that controls
the selection between the different sources.
Address: Base + 0x0500–0x0528 (11 registers) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PADSEL0
0 0 0 0
PADSEL1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0
PADSEL2
0 0 0 0
PADSEL3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 37-12. Pad Selection for Multiplexed Inputs Register (PSMI0_3)
Table 37-11. PSMI0_3 field descriptions
Field Description
PADSEL0–3,
PADSEL4–7,
...
PADSEL28–31
Pad Selection Bits
Each PADSEL field selects the pad currently used for a certain input function. See Tabl e 37-12.
Table 37-12. Peripheral input pin selection
PSMI register SIUL address offset Peripheral input
Mapping of input pin to
peripheral input
1
PSMI[0] 0x500 CAN0_RXD 0: PCR[17]
1: PCR[109]
PSMI[1] 0x501 CAN1_RXD 0: PCR[26]
1: PCR[83]
2: PCR[111]
PSMI[2] 0x502 DCU_PDI[0] 0: PCR[17]
1: PCR[109]
PSMI[3] 0x503 DCU_PDI[1] 0: PCR[16]
1: PCR[110]
PSMI[4] 0x504 DCU_PDI[2] 0: PCR[26]
1: PCR[111]
PSMI[5] 0x505 DCU_PDI[3] 0: PCR[27]
1: PCR[112]