NXP Semiconductors MPC5606S - Page 1341

Revision History
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1339
Clock Description In the “Clock architecture” section, changed “FMPLL1 clocked by Main XOSC, only for
eMIOSA, eMIOSB, and DCU clock” to “FMPLL1 clocked by Main XOSC, only for
eMIOSA, eMIOSB, QuadSPI, and DCU clock”.
Renamed eMIOS_A and eMIOS_B to eMIOS_0 and eMIOS_1, respectively.
Replaced the “System Clock Generation” diagram.
Added an “Auxiliary clocks” section.
Added the “Peripheral clock generation registers” table to the “Clock gating” section.
Removed references to “Cut1” and “Cut2”.
Replaced the second paragraph of the “Clock Gating” section.
Replaced the entire CGM section.
In the “Main features” list of the XOSC external oscillator, deleted “Oscillator powerdown
control and status” (it is a feature of the MC_ME, not the XOSC).
In the “Functional description” of the XOSC external oscillator, deleted the information on
the unsupported “Standalone control by OSC_CTL register”.
Changed bits 30 and 31 of the OSC_CTL register to Reserved.
In the “32 kHz OSC digital interface” section, deleted “The implementation of OSCON,
S_OSC bits in OSC_CTL register depends on the parameter OSC_ON_STAT value” (the
bits are implemented on this device).
Revised the truth table In the “32 kHz OSC digital interface” section.
Revised the “Low Power RC Oscillator (128 kHz)” section to reflect the fact that this
oscillator remains on in all modes.
Deleted the LPRC_CTL[LPRCON_STDBY] bit.
Deleted the second paragraph of the FMPLL0/1 Overview section.
In the FMPLL0/1 section, changed the reset value of CR[ODF] (was 0, is 1).
In the FMPLL0/1 section, added text to clarify that 1:1 mode is for FMPLL0 only.
In the CMU memory map, renamed CMU_FDISP to CMU_FDR.
Revised the “PLL clock monitor” section.
Mode Entry Module Replaced the entire chapter.
Boot Assist Module Added “System can recover from Static mode only by Reset” to the Features section.
Changed “LINFlex_A” to “LINFlex 0”.
In the RCHW section, changed “Each boot sector contains at offset 0x02” to “Each boot
sector contains at offset 0x00”.
Changed the position of the RCHW in the “Flash memory partitioning and RCHW search”
figure.
Added “SWT (the BAM disables it)” to the “BAM resources” section.
Power Control Unit Replaced the entire chapter.
Reset Generation
Module
Replaced the entire chapter.
e200z0h Core Renamed the chapter (was “e200z0 Core”, is “e200z0h Core”).
Added a module boundary to the block diagram.
In the block diagram, changed “MEMORY MANAGEMENT UNIT” to “NEXUS DEBUG
UNIT”.
Removed erroneous references to the z1 core.
Enhanced Direct
Memory Access
Corrected the bit ordering in the register diagrams.
DMA Channel Mux Added this chapter to the document.
Crossbar Switch Revised the block diagram.
Table C-6. Changes between revisions 1 and 2 (continued)
Chapter Description