Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 259
Figure 9-21. Single Action Input Capture with rising edge triggering example
Figure 9-22. Single Action Input Capture with both edges triggering example
9.5.1.1.3 Single Action Output Compare (SAOC) mode
In SAOC mode (MODE[0:6]=0000011), a match value is loaded in register A2 and then immediately
transferred to register A1 to be compared with the selected time base. When a match occurs, the EDSEL
bit selects whether the output flip-flop is toggled or the value in EDPOL is transferred to it. Along with
the match the FLAG bit is set to indicate that the output compare match has occurred. Writing to register
EMIOSA[n] stores the value in register A2, and reading register EMIOSA[n] returns the value of register
A1.
An output compare match can be simulated in software by setting the FORCMA bit in the EMIOSC[n]
register. In this case, the FLAG bit is not set.
When SAOC mode is entered coming out of GPIO mode, the output flip-flop is set to the complement of
the EDPOL bit in the EMIOSC[n] register.
The counter bus can be either internal or external and is selected through BSL[0:1] bits.
Figure 9-23 and Figure 9-24 show how the Unified Channel can be used to perform a single output
compare with the EDPOL value being transferred to the output flip-flop and toggling the output flip-flop
at each match, respectively. Note that once in SAOC mode the matches are enabled; thus the desired match
value on register A1 must be written before the mode is entered. A1 register can be updated at any time,
thus modifying the match value which will be reflected in the output signal generated by the channel.
selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016A0
FLAG pin/register
A2 (captured) value
2
0xxxxxxx 0x001000 0x001250 0x0016A0
input signal
1
Edge detect Edge detect
Edge detect
Notes: 1. After input filter
2. EMIOSA[n] <= A2
EDSEL = 0
EDPOL = 1
selected counter bus 0x001000 0x001102
FLAG set event
A2 (captured) value
2
0xxxxxxx 0x001000
input signal
1
Edge detect
Notes: 1. After input filter
2. EMIOSA[n] <= A2
0x001103 0x0011080x001104 0x001105 0x001106 0x0011070x001001
FLAG pin/register
Edge detect
FLAG clear
Edge detect
0x001103 0x001108
EDSEL = 1
EDPOL = x
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