NXP Semiconductors MPC5606S - Page 262

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
260 Freescale Semiconductor
Subsequent matches are enabled with no need of further writes to the EMIOSA[n] register. The FLAG is
set at the same time a match occurs.
NOTE
The channel internal counter in SAOC mode is free-running. It starts
counting as soon as SAOC mode is entered.
Figure 9-23. SAOC example with EDPOL value being transferred to the output flip-flop
Figure 9-24. SAOC example toggling the output flip-flop
9.5.1.1.4 Modulus Counter Buffered (MCB) mode
The MCB mode provides a time base which can be shared with other channels through the internal counter
buses. Register A1 is double-buffered, thus allowing smooth transitions between cycles when changing
the value of the A2 register on the fly. The A1 register is updated at the cycle boundary, which is defined
as when the internal counter transitions to 0x1.
selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000
output flip-flop
Update to A1
A1 value
1
0xxxxxxx 0x001000
FLAG pin/register
0x001000 0x001000 0x001000
A1 match
A1 match A1 match
Notes: 1. EMIOSA[n] = A2
EDSEL = 0
EDPOL = 1
A2 = A1 according to OU[n] bit
selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000
A1 value
1
0xxxxxxx 0x001000
output flip-flop
Update to A1
FLAG pin/register
A1 match
A1 match A1 match
0x001000 0x001000
0x001000
Notes: 1. EMIOSA[n] = A2
EDSEL = 1
EDPOL = x
A2 = A1 according to OU[n] bit
selected counter bus 0x0 0x2
FLAG set event
A2 value
1
0x1
output flip-flop
Note: 1. EMIOSA[n] <= A2
0x0 0x20x1 0x2 0x0 0x10x1
FLAG pin/register
FLAG clear
EDSEL = 1
System Clock
A1 match
EDPOL = x