Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 261
The internal counter values operate within a range from 0x1 up to the value of the A1 register. If when
entering MCB mode coming out of GPIO mode, the internal counter value is not within that range, then
the A match will not occur. This will cause the channel internal counter to wrap at the maximum counter
value, which is 0xFFFF for a 16-bit counter. After the counter wrap occurs, it returns to 0x1 and resumes
normal MCB mode operation. Thus in order to avoid the counter wrap condition, make sure the internal
counter value is within the 0x1 to A1 register value range when MCB mode is entered.
The MODE[6] bit selects the internal clock source if cleared, or external if set. When the external clock is
selected, the input channel pin is used as the channel clock source. The active edge of this clock is defined
by the EDPOL and EDSEL bits in the EMIOSC[n] channel register.
When entering MCB mode, if the up counter is selected by MODE[4]=0 (MODE[0:6]=101000b), the
internal counter starts counting up from its current value until a match with A1 occurs. The internal counter
is set to 0x1 when its value matches the A1 value and a clock tick occurs (either prescaled clock or input
pin event).
If the up/down counter is selected by setting MODE[4]=1, the counter changes direction at A1 match and
counts down until it reaches the value 0x1. After it has reached 0x1, it is set to count up again. The B1
register is used to generate a match in order to set the internal counter in the up-count direction if up/down
mode is selected. Register B1 cannot be changed while this mode is selected.
Note that MCB mode counts between 0x1 and the value in the A1 register. Only values greater than 0x1
may be written to the A1 register. Loading any other values leads to unpredictable results. The counter
cycle period is equal to the A1 value in up counter mode. If in up/down counter mode, the period is defined
by the expression (2 × A1) – 2.
Figure 9-25 shows the counter cycle for several possible A1 values. Register A1 is loaded with the A2
register value at the cycle boundary. Thus, any value written to the A2 register within cycle n will be
updated to A1 at the next cycle boundary, and therefore will be used on cycle n + 1. The cycle boundary
between cycle n and cycle n + 1 is defined as when the internal counter transitions from the A1 value in
cycle n to 0x1 in cycle n + 1. Note that the FLAG is generated at the cycle boundary and has a synchronous
operation, meaning that it is asserted one system clock cycle after the FLAG set event.
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