NXP Semiconductors MPC5606S - Page 264

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
262 Freescale Semiconductor
Figure 9-25. Modulus Counter Buffered (MCB) up count mode
Figure 9-26 shows the MCB in up/down counter mode (MODE[0:6]=10101bb). The A1 register is
updated at the cycle boundary. If A2 is written in cycle n, this new value will be used in cycle n + 1 for A1
match. Flags are generated only at A1 match start if MODE[5] is 0. If MODE[5] is set to 1, flags are also
generated at the cycle boundary.
Figure 9-26. Modulus Counter Buffered (MCB) up/down mode
Figure 9-27 describes in more detail the A1 register update process in up counter mode. The A1 load signal
is generated at the last system clock period of a counter cycle. Thus, A1 is updated with the A2 value at
the same time that the counter (EMIOSCNT[n]) is loaded with 0x1. The load signal pulse has the duration
of one system clock period. If A2 is written within cycle n + 1, its value is available at A1 at the first clock
of cycle n + 1, and the new value is used for match at cycle n + 1. The update disable bits OU[n] of the
EMIOSOUDIS register can be used to control the update of this register, thus allowing delay of the A1
register update for synchronization purposes.
EMIOSCNT[n]
TIME
write to A2 match A1 match A1 match A1
write to A2
0x000001
0x000005
0x000006
0x000007
FLAG set event
A1 value
0x000006
0x000005
0x000007
0x000007
0x000005 0x000007
A2 value
FLAG pin/register
Prescaler ratio = 1
cycle n
cycle n+1 cycle n+2
FLAG clear
EMIOSCNT[n]
TIME
write to A2
match A1
match A1
write to A2
0x000001
0x000005
0x000006
0x000007
FLAG set event
A1 value
0x000006 0x000005 0x000007
0x000005 0x000007
A2 value
FLAG pin/register
Prescaler ratio = 1
cycle n+1
cycle n+2cycle n
FLAG clear